deint_v2mult_4l.v

Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序

//-----------------------------------------------------------------
// deint_v2mult_4L.v - Video Scan Line De-interlacing
//               Virtex-II Video Demo Board
//
//
//
//
//                  Author: Gregg C. Hawkes
//                  Senior Staff Applications Engineer
//
//                  Video Applications
//                  Advanced Products Division
//                  Xilinx, Inc.
//
//                  Copyright (c) 1999 Xilinx, Inc.
//                  All rights reserved
//
//                  Date:   Aug. 6, 2001
//                  For:    Video Demo Board
//
//                  RESTRICTED RIGHTS LEGEND
//
//      This software has not been published by the author, and 
//      has been disclosed to others for the purpose of enhancing 
//      and promoting design productivity in Xilinx products.
//
//      Therefore use, duplication or disclosure, now and in the 
//      future should give consideration to the productivity 
//      enhancements afforded the user of this code by the author's 
//      efforts.  Thank you for using our products !
//
// Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//
// 
// Revision:
//          Aug. 6, 2001     Creation
//
//
// Other modules instanced in this design:
//
//          none
/*

BRIEF DESCRIPTION 

One of the more frequent video conversions needed between various
consumer video input devices, video processing, and output devices is
interlaced to non-interlaced conversion. This process is sometimes
called de-interlacing, scan-line doubling, or progressive scanning. This
application note and reference design provides technical details
surrounding video de-interlace and how it is implemented in the
MicroBlaze and multimedia demo board. 

DETAILED DESCRIPTION 

An entire picture, or frame, requires two passes of the electron beam
across the face of a display. Each of these events is termed one field.
Interlaced video draws the odd lines in a frame (the odd field) followed
by the even field. Historically, this concept allowed the overall pixel
storage to be reduced by a factor of two over frame rate approaches
requiring all of the lines to be drawn every frame. Although it results
in cheaper displays, PC boards, and digital logic designs, the downside
of this method is noticeable flicker and other artifacts. 

Methods to recreate the lines between field lines usually involve
interpolation within a field. Better results can be acheived by
interpolating two fields of data or taking into account motion, but this
module deals with only a single set of field lines. 4 lines are
interpolated to produce the "phantom line". 



Design Information for V2 Multiplier version
--------------------------------------------
xc2v1000-ff896-6

MULT18X18s:   6   15%
BRAMs         6   15%
Slices      376    7%
FFs         556    5%
LUTs        156    1%
IO          100   22%
gates   423,149

Minimum period:   9.982ns (Maximum frequency: 100 MHz)
Maximum net delay:   4.127ns


Note: Using coregen the V2 Mults can be replaced with parallel, 10 bit
signed integer X 12 bit coefficients for roughly 68 LUTs and 34
Registers each. This alternative would save the high performance V2
Multipliers for other uses or allow the design to directly map to
SPARTAN families.

*/



`timescale 1ns / 100ps



module deint_v2mult_4L (
rst,             // resets input data register and control
clk,             // video component rate clock, 27Mhz for SDTV

Fi,              // Low to High signals start of Field One
Vi,              // High signals Vertical Blanking
Hi,              // High signals Horizontal Blanking

Fo,              // Field signal delayed by pipe length
Vo,              // Vertical signal delayed by pipe length
Ho,              // Horizontal signal delayed by pipe length

cei,             // input component rate is 1/2 the clock rate
ceo,             // output component rate is 1/2 the clock rate

R_in,            // video component in, I[8].F[2], twos complement
G_in,            // video component in, I[8].F[2], twos complement
B_in,            // video component in, I[8].F[2], twos complement

R_out_real,      // video component out, I[8].F[2], twos complement, clamped
G_out_real,      // video component out, I[8].F[2], twos complement, clamped
B_out_real,      // video component out, I[8].F[2], twos complement, clamped

R_out_filt,      // video component out, I[8].F[2], twos complement, clamped
G_out_filt,      // video component out, I[8].F[2], twos complement, clamped
B_out_filt,      // video component out, I[8].F[2], twos complement, clamped
);

parameter PIPE_LENGTH = 2;

input rst, clk;

input Hi, Vi, Fi, cei;

input[9:0] R_in, G_in, B_in;

output [9:0]  R_out_real, G_out_real, B_out_real;
output [9:0]  R_out_filt, G_out_filt, B_out_filt;

output Ho, Vo, Fo, ceo;

reg [PIPE_LENGTH-1:0] H_rg, V_rg, F_rg, ce_rg;
wire Fo, Vo, Ho, ceo;

reg [9:0] R_rg, G_rg, B_rg;

reg [10:0] lb_adr;
wire [15:0] LB1_hi_DIA, LB1_lo_DIA,
            LB1_hi_DOA, LB1_lo_DOA, 
            LB2_hi_DOA, LB2_lo_DOA,
            LB3_hi_DOA, LB3_lo_DOA;

reg [9:0] FR_rg [3:0];
reg [9:0] FG_rg [3:0];
reg [9:0] FB_rg [3:0];

reg [10:0] R_pre_add0, G_pre_add0, B_pre_add0, 
           R_pre_add1, G_pre_add1, B_pre_add1; 

wire [35:0] PR0, PR1, PG0, PG1, PB0, PB1;

reg [35:0] PR0_rg, PR1_rg, PG0_rg, PG1_rg, PB0_rg, PB1_rg;

reg [11:0] R_filt, G_filt, B_filt;

reg [9:0] R_correct, B_correct, G_correct;
reg [9:0] R_dld1, G_dld1, B_dld1, 
          R_dld2, G_dld2, B_dld2,
          R_dld3, G_dld3, B_dld3,
          R_dld4, G_dld4, B_dld4;

reg [9:0] R_out_real, G_out_real, B_out_real;
reg [9:0] R_out_filt, G_out_filt, B_out_filt;

integer i;


//-----------------------------------------------------------------------
//
// Pipeline H, V, and F.
//
always @ (posedge clk) begin
  if (rst) begin H_rg <= 0; V_rg <= 0; F_rg <= 0; end
  else begin
    F_rg[PIPE_LENGTH-1:0] <= {F_rg[PIPE_LENGTH-2:0], Fi};
    V_rg[PIPE_LENGTH-1:0] <= {V_rg[PIPE_LENGTH-2:0], Vi};
    H_rg[PIPE_LENGTH-1:0] <= {H_rg[PIPE_LENGTH-2:0], Hi};
    ce_rg[PIPE_LENGTH-1:0] <= {ce_rg[PIPE_LENGTH-2:0], cei};
  end
end

assign Fo = F_rg[PIPE_LENGTH-1];
assign Vo = V_rg[PIPE_LENGTH-1];
assign Ho = H_rg[PIPE_LENGTH-1];
assign ceo = ce_rg[PIPE_LENGTH-1];



//-----------------------------------------------------------------------
//
// Register the input data stream
//
always @ (posedge clk) begin
  if (rst) begin R_rg <= 0; G_rg <= 0; B_rg <= 0; end
  else if (cei) begin R_rg <= R_in; G_rg <= G_in; B_rg <= B_in; end
  else begin R_rg <= R_rg; G_rg <= G_rg; B_rg <= B_rg; end
end


//-----------------------------------------------------------------------
//
// The line buffer address drives all of the line buffers.  It counts 
// up at a 13.5 Mhz rate.
/*
When blanking asserts the BRAM input addresses are held at zero. If no
blanking the address counts up until the line length of 719 has been
reached, then back to zero.
*/
always @ (posedge clk) begin
  if (rst | H_rg[0] | V_rg[0]) lb_adr <= 0;
  else if (ce_rg[1]) lb_adr <= lb_adr + 1;
  else lb_adr <= lb_adr;
end



//-----------------------------------------------------------------------
//
// 3 Line buffers follow.  Stream 0 to the filter comes directly from the
// input.
/*
Each BRAM (15 bits of data per BRAM) forms 1/2 of a pixel line buffer (3
components = 30 bits). The memory requirement is 720 pixels by 30 bits.
The read and the write address is the same. Read before write mode is
used allowing memory data to be presented and held at the outputs while
write data enters the RAM. (attribute numbers are in hex)
*/

assign LB1_hi_DIA = {1'b0, R_rg[9:5], G_rg[9:5], B_rg[9:5]};
assign LB1_lo_DIA = {1'b0, R_rg[4:0], G_rg[4:0], B_rg[4:0]};


//-----------------------------------------------------------------------
//
// Line Buffer LB1
//
// synthesis attribute WRITE_MODE_A of LB1_hi is "READ_FIRST"
// synthesis attribute WRITE_MODE_B of LB1_hi is "READ_FIRST"
// synthesis attribute INIT_A of LB1_hi is "000000000"
// synthesis attribute INIT_B of LB1_hi is "000000000"
// synthesis attribute SRVAL_A of LB1_hi is "000000000"
// synthesis attribute SRVAL_B of LB1_hi is "000000000"
//
RAMB16_S18_S18  LB1_hi (
.DOA(LB1_hi_DOA),
.DOPA(),
.DOB(),
.DOPB(),
.ADDRA(lb_adr[10:1]),
.CLKA(clk),
.DIA(LB1_hi_DIA),
.DIPA(2'b00),
.ENA(ce_rg[1]),
.SSRA(1'b0),
.WEA(ce_rg[1]),
.ADDRB(10'h000),
.CLKB(clk),
.DIB(16'h0000),
.DIPB(2'b00),
.ENB(1'b1),
.SSRB(rst),
.WEB(1'b0)
);

// synthesis attribute WRITE_MODE_A of LB1_lo is "READ_FIRST"
// synthesis attribute WRITE_MODE_B of LB1_lo is "READ_FIRST"
// synthesis attribute INIT_A of LB1_lo is "000000000"
// synthesis attribute INIT_B of LB1_lo is "000000000"
// synthesis attribute SRVAL_A of LB1_lo is "000000000"
// synthesis attribute SRVAL_B of LB1_lo is "000000000"
//
RAMB16_S18_S18  LB1_lo (
.DOA(LB1_lo_DOA),
.DOPA(),
.DOB(),
.DOPB(),
.ADDRA(lb_adr[10:1]),
.CLKA(clk),
.DIA(LB1_lo_DIA),
.DIPA(2'b00),
.ENA(ce_rg[1]),
.SSRA(1'b0),
.WEA(ce_rg[1]),
.ADDRB(10'h000),
.CLKB(clk),
.DIB(16'h0000),
.DIPB(2'b00),
.ENB(1'b1),
.SSRB(rst),
.WEB(1'b0)
);




//-----------------------------------------------------------------------
//
// Line Buffer LB2
//
// synthesis attribute WRITE_MODE_A of LB2_hi is "READ_FIRST"
// synthesis attribute WRITE_MODE_B of LB2_hi is "READ_FIRST"
// synthesis attribute INIT_A of LB2_hi is "000000000"
// synthesis attribute INIT_B of LB2_hi is "000000000"
// synthesis attribute SRVAL_A of LB2_hi is "000000000"
// synthesis attribute SRVAL_B of LB2_hi is "000000000"
//
RAMB16_S18_S18  LB2_hi (
.DOA(LB2_hi_DOA),
.DOPA(),
.DOB(),
.DOPB(),
.ADDRA(lb_adr[10:1]),
.CLKA(clk),
.DIA(LB1_hi_DOA),
.DIPA(2'b00),
.ENA(ce_rg[1]),
.SSRA(1'b0),
.WEA(ce_rg[1]),
.ADDRB(10'h000),
.CLKB(clk),
.DIB(16'h0000),
.DIPB(2'b00),
.ENB(1'b1),
.SSRB(rst),
.WEB(1'b0)
);

// synthesis attribute WRITE_MODE_A of LB2_lo is "READ_FIRST"
// synthesis attribute WRITE_MODE_B of LB2_lo is "READ_FIRST"
// synthesis attribute INIT_A of LB2_lo is "000000000"
// synthesis attribute INIT_B of LB2_lo is "000000000"
// synthesis attribute SRVAL_A of LB2_lo is "000000000"
// synthesis attribute SRVAL_B of LB2_lo is "000000000"