mult_model.v

YUV转RGB的源程序

/**************************************************************************
 ** 
 ** Module: YCrCb2RGB
 **
 ** Instantiated Multiplier:
 ***************************************************************************/

//'include "c:/xilinx/verilog/src/unisims/mult18x18.v"

module YCrCb2RGB ( R, G, B, clk, rst, Y, Cr, Cb );

output [7:0]  R, G, B;

input clk,rst;
input[9:0] Y, Cr, Cb;

//1.164 = 01.00101001
//1.596 = 01.10011000
//0.813 = 00.11010000
//0.392 = 00.01100100
//2.017 = 10.00000100

wire [10:0] Y_int, Cr_int, Cb_int;
reg [12:0] R_int1;
reg [12:0] G_int1;
reg [12:0] B_int1;
reg [12:0] R_int2;
reg [12:0] G_int2;
reg [12:0] B_int2;
reg [9:0] Y_reg, Cr_reg, Cb_reg;
//reg [10:0] Y_reg, Cr_reg, Cb_reg;
reg [17:0] const1,const2,const3,const4,const5;

wire [35:0] P1,P2,P3,P4,P5;
reg [11:0] P1_int,P2_int,P3_int,P4_int,P5_int;
wire [12:0] P1_int_act,P2_int_act,P3_int_act,P4_int_act,P5_int_act;
reg sign_y1,sign_cr1,sign_cb1,sign_y2,sign_cr2,sign_cb2;

wire[17:0] Y_reg_in, Cr_reg_in, Cb_reg_in;

assign Y_int = Y - 'd64;
assign Cr_int = Cr - 'd512;
assign Cb_int = Cb - 'd512;

//save signs of above internal signals
always @ (posedge clk or posedge rst)
if (rst)
      begin
       sign_y1 <= 0; sign_cr1 <= 0; sign_cb1 <= 0;
       sign_y2 <= 0; sign_cr2 <= 0; sign_cb2 <= 0;
      end
else  
      begin
       sign_y1 <= Y_int[10]; sign_cr1 <= Cr_int[10]; sign_cb1 <= Cb_int[10];
       sign_y2 <= sign_y1; sign_cr2 <= sign_cr1; sign_cb2 <= sign_cb1;
      end



// 2's complement logic 

always @ (posedge clk or posedge rst)
if (rst)
      begin
       Y_reg <= 0; Cr_reg <= 0; Cb_reg <= 0;
      end
else  
      begin
         if (Y_int[10] )
             Y_reg <= (-Y_int);//if negative take complement ie., absolute value
         else
             Y_reg <= Y_int;
         if (Cr_int[10])
             Cr_reg <= (-Cr_int);//if negative take complement ie., absolute value
         else
             Cr_reg <= Cr_int;
         if (Cb_int[10])
             Cb_reg <= (-Cb_int);//if negative take complement ie., absolute value
         else
             Cb_reg <= Cb_int ;
      end


always @ (posedge clk)
begin
 const1 = 18'b 0100101010;
 const2 = 18'b 0110011000;
 const3 = 18'b 0011010000;
 const4 = 18'b 0001100100;
 const5 = 18'b 1000000100;
end

MULT18X18 U1_MULT18X18 ( .A(const1), .B({8'b00000000,Y_reg}), .P(P1)); // 1.164(Y-64) = 01.00101001(Y-64)
MULT18X18 U2_mult18x18 ( .A(const2), .B({8'b00000000,Cr_reg}), .P(P2)); // 1.596(Cr-512) = 01.10011000(Cr-512)
MULT18X18 U3_mult18x18 ( .A(const3), .B({8'b00000000,Cr_reg}), .P(P3)); // 0.813(Cr-512) = 00.11010000(Cr-512)
MULT18X18 U4_mult18x18 ( .A(const4), .B({8'b00000000,Cb_reg}), .P(P4)); // 0.392(Cb-512) = 00.01100100(Cb-512)
MULT18X18 U5_mult18x18 ( .A(const5), .B({8'b00000000,Cb_reg}), .P(P5)); // 2.017(Cb-512) = 10.00000100(Cb-512)


/* 10 bits * 10 bits gives 20 bit products. 8 LSBs ignored */
always @ (posedge clk or posedge rst)
if (rst)
      begin
       P1_int <= 0; P2_int <= 0; P3_int <= 0; P4_int <= 0; P5_int <= 0;
      end
else  
       begin
       P1_int <= P1[19:8]; P2_int <= P2[19:8]; P3_int <= P3[19:8]; P4_int <= P4[19:8]; P5_int <= P5[19:8];
      end

assign P1_int_act = (sign_y2) ? (-P1_int) : P1_int; // if product is negative, take 2's compl.
assign P2_int_act = (sign_cr2) ? (-P2_int) : P2_int; // if product is negative, take 2's compl.
assign P3_int_act = (sign_cr2) ? (-P3_int) : P3_int; // if product is negative, take 2's compl.
assign P4_int_act = (sign_cb2) ? (-P4_int) : P4_int; // if product is negative, take 2's compl.
assign P5_int_act = (sign_cb2) ? (-P5_int) : P5_int; // if product is negative, take 2's compl.




always @ (posedge clk or posedge rst)
   if (rst)
      begin
       R_int1 <= 0; G_int1 <= 0; B_int1 <= 0;
       R_int2 <= 0; G_int2 <= 0; B_int2 <= 0;
      end
   else  
     begin
      R_int1 <= {P1_int_act} + {P2_int_act};
      G_int1 <= {P1_int_act} - {P3_int_act};
      B_int1 <= {P1_int_act} + {P5_int_act};
      R_int2 <= R_int1;
      G_int2 <= G_int1 - {P4_int_act};
//G_int2 <= {P1_int_act} - {P3_int_act} - {P4_int_act};
      B_int2 <= B_int1;
     end



/* output limiter . Limit output to 0 if Rint,Gint and Bint < 0 and
limit output to 4095(1111,1111,1111) if Rint,Gint and Bint > 4095 */

assign R =  R_int2[12] ? 8'b0 : (R_int2[11:10] == 2'b0) ? R_int2[9:2] : 8'b11111111;
assign G =  G_int2[12] ? 8'b0 : (G_int2[11:10] == 2'b0) ? G_int2[9:2] : 8'b11111111;
assign B =  B_int2[12] ? 8'b0 : (B_int2[11:10] == 2'b0) ? B_int2[9:2] : 8'b11111111;




endmodule

module MULT18X18 (A, B, P); // synthesis syn_black_box
input [17:0]A;
input [17:0]B;
output [35:0]P;


endmodule