mult_model.vhd

YUV转RGB的源程序

--/**************************************************************************
-- ** 
-- ** Module: ycrcb2rgb
-- **
-- ** Instantiated Multiplier:
-- ***************************************************************************/

library IEEE; 
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
-- include the following for synthesis only
--library virtex; 
--use virtex.components.all; 
--library synplify; 
--use synplify.attributes.all; 
library unisims_ver; -- include this for modelsim simulation
                     -- when using mult18x18


entity ycrcb2rgb is
  port (Y,Cr,Cb : in std_logic_vector(9 downto 0); 
        clk,rst : in std_logic;
          R,G,B : out std_logic_vector(7 downto 0));
end ycrcb2rgb ;

architecture multmodel of ycrcb2rgb is

-- Signal Declarations:

--signal logic1, logic0 : std_logic;
signal Y_int, Cr_int, Cb_int: std_logic_vector(10 downto 0);
signal sign_y1, sign_cr1, sign_cb1 : std_logic;
signal sign_y2, sign_cr2, sign_cb2 : std_logic;
signal Y_reg, Cr_reg, Cb_reg: std_logic_vector(10 downto 0);
signal R_int1, G_int1, B_int1: std_logic_vector(12 downto 0);
signal R_int2, G_int2, B_int2: std_logic_vector(12 downto 0);
signal P1_int,P2_int,P3_int,P4_int,P5_int: std_logic_vector(12 downto 0);
signal P1_int_act,P2_int_act,P3_int_act,P4_int_act,P5_int_act: std_logic_vector(12 downto 0);
signal sign_ext_y, sign_ext_cr, sign_ext_cb : std_logic_vector(17 downto 0);
signal check1,check2: std_logic_vector (17 downto 0);
signal P1,P2,P3,P4,P5: std_logic_vector(35 downto 0);
signal const1: std_logic_vector(17 downto 0) := "000000000100101011"; -- 1.164 = 01.00101001
signal const2: std_logic_vector(17 downto 0) := "000000000110011000"; -- 1.596 = 01.10011000
signal const3: std_logic_vector(17 downto 0) := "000000000011010000"; -- 0.813 = 00.11010000
signal const4: std_logic_vector(17 downto 0) := "000000000001100100"; -- 0.392 = 00.01100100
signal const5: std_logic_vector(17 downto 0) := "000000001000000100"; -- 2.017 = 10.00000100


component MULT18X18 
port(
A,B: in std_logic_vector (17 downto 0);
P: out std_logic_vector (35 downto 0));
end component;



begin

Y_int <= (('0' & Y) - "00001000000"); 
Cr_int <= (('0' & Cr) - "01000000000");
Cb_int <= (('0' & Cb) - "01000000000");

-- save sign
PA:process (clk,rst)
  begin
   if (rst = '1') then
       sign_y1 <= '0'; sign_cr1 <= '0'; sign_cb1 <= '0';
       sign_y2 <= '0'; sign_cr2 <= '0'; sign_cb2 <= '0';
elsif (rising_edge (clk)) then
       sign_y1 <= Y_int(10); sign_cr1 <= Cr_int(10); sign_cb1 <= Cb_int(10);
       sign_y2 <= sign_y1; sign_cr2 <= sign_cr1; sign_cb2 <= sign_cb1;
      end if;
end process PA;



--Y_int <= (('0' & Y_reg) - "00001000000"); 
--CR_int <= (('0' & CR_reg) - "01000000000");
--CB_int <= (('0' & CB_reg) - "01000000000");

-- 2's complement logic 
PB:process (clk,rst)
  begin
   if (rst = '1') then
     Y_reg <= (others => '0'); 
	  Cr_reg <= (others => '0'); 
	  Cb_reg <= (others => '0');
   elsif (rising_edge (clk)) then
      
        if (Y_int(10) = '0')  then
        Y_reg <= Y_int;
        else
        Y_reg <= not(Y_int) + 1;
      end if;
      
        if (Cr_int(10) = '0') then
        Cr_reg <= Cr_int;
        else
        Cr_reg <= not(Cr_int) +1;
      end if;
     
        if (Cb_int(10) = '0') then
        Cb_reg <= Cb_int;
        else
        Cb_reg <= not(Cb_int) +1;
     end if;
   end if;
  end process PB;

--const1 = "000000000100101001";
--const2 = "000000000110011000";
--const3 = "000000000011010000";
--const4 = "000000000001100100";
--const5 = "000000001000000100";
sign_ext_y <= "0000000" & Y_reg;
sign_ext_cr <= "0000000"& Cr_reg;
sign_ext_cb <= "0000000" & Cb_reg;

check1 <= const1;
check2 <= sign_ext_y;
-- 1.164(Y-64) = 01.00101001(Y-64)
--MULT1: MULT18X18 port map( A => const1, B => sign_ext_y, P => P1);
-- 1.596(Cr-512) = 01.10011000(Cr-512)
--MULT2: MULT18X18 port map( A => const2, B => sign_ext_cr, P => P2);
-- 0.813(Cr-512) = 00.11010000(Cr-512)
--MULT3: MULT18X18 port map( A => const3, B => sign_ext_cr, P => P3);
-- 0.392(Cb-512) = 00.01100100(Cb-512)
--MULT4: MULT18X18 port map( A => const4, B => sign_ext_cb, P => P4);
-- 2.017(Cb-512) = 10.00000100(Cb-512)
--MULT5: MULT18X18 port map( A => const5, B => sign_ext_cb, P => P5); 

mult1a: MULT18X18 port map (A => const1, B => sign_ext_y, P => P1);
mult2a: MULT18X18 port map (A => const2, B => sign_ext_cr, P => P2);
mult3a: MULT18X18 port map (A => const3, B => sign_ext_cr, P => P3);
mult4a: MULT18X18 port map (A => const4, B => sign_ext_cb, P => P4);
mult5a: MULT18X18 port map (A => const5, B => sign_ext_cb, P => P5);

PC:process (clk,rst)
begin
if (rst = '1') then
      P1_int <= (others => '0'); P2_int <= (others => '0'); 
      P3_int <= (others => '0'); P4_int <= (others => '0'); 
      P5_int <= (others => '0');
elsif (rising_edge (clk)) then
      P1_int <= P1(20 downto 8); P2_int <= P2(20 downto 8); 
      P3_int <= P3(20 downto 8); P4_int <= P4(20 downto 8); 
      P5_int <= P5(20 downto 8);
end if;
end process PC;

 P1_int_act <= (not(P1_int) + '1') when (sign_y2='1') else P1_int; -- if product is negative, take 2's compl.
 P2_int_act <= (not(P2_int) + '1') when (sign_cr2='1') else P2_int; -- if product is negative, take 2's compl.
 P3_int_act <= (not(P3_int) + '1') when (sign_cr2='1') else P3_int; -- if product is negative, take 2's compl.
 P4_int_act <= (not(P4_int) + '1') when (sign_cb2='1') else P4_int; -- if product is negative, take 2's compl.
 P5_int_act <= (not(P5_int) + '1') when (sign_cb2='1') else P5_int; -- if product is negative, take 2's compl.

PD:process (clk,rst)
  begin
   if (rst = '1') then
      R_int1 <= (others => '0'); R_int2 <= (others => '0');
	   G_int1 <= (others => '0'); G_int2 <= (others => '0');
	   B_int1 <= (others => '0'); B_int2 <= (others => '0');
   elsif (rising_edge (clk)) then
      R_int1 <= P1_int_act + P2_int_act;
      G_int1 <= P1_int_act - P3_int_act;
      G_int2 <= G_int1 - P4_int_act;
	    B_int1 <= P1_int_act + P5_int_act;
      R_int2 <= R_int1;
      B_int2 <= B_int1;
   end if;
  end process PD;

-- output limiter. Limit output to '0' if R_int2,G_int2,B_int2 < 0  and lilmit ouput
--to 4095 (1111,1111,1111) if R_int2,G_int2,B_int2 > 4095.

      R <= "00000000" when (R_int2(12) = '1') 
           else R_int2(9 downto 2) when (R_int2(11 downto 10) = "00") 
           else "11111111";
      G <= "00000000" when (G_int2(12) = '1') 
           else G_int2(9 downto 2) when (G_int2(11 downto 10) = "00") 
           else "11111111";
      B <= "00000000" when (B_int2(12) = '1') 
           else B_int2(9 downto 2) when (B_int2(11 downto 10) = "00") 
           else "11111111";

end multmodel;