kcpsm2_int_test.vhd

Xillinx 的8位MCU软核的源代码

--
-- Interrupt test for KCPSM-II 
--
-- Ken Chapman - Xilinx Ltd - February 2002
--
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
------------------------------------------------------------------------------------
--
--
entity kcpsm2_int_test is
    Port (         counter : out std_logic_vector(7 downto 0);
                 waveforms : out std_logic_vector(7 downto 0);
           interrupt_event : in std_logic;
                       clk : in std_logic);
    end kcpsm2_int_test;
--
------------------------------------------------------------------------------------
--
-- Start of test achitecture
--
architecture Behavioral of kcpsm2_int_test is
--
------------------------------------------------------------------------------------
--
-- declaration of KCPSM2
--
  component kcpsm2 
    Port (      address : out std_logic_vector(9 downto 0);
            instruction : in std_logic_vector(17 downto 0);
                port_id : out std_logic_vector(7 downto 0);
           write_strobe : out std_logic;
               out_port : out std_logic_vector(7 downto 0);
            read_strobe : out std_logic;
                in_port : in std_logic_vector(7 downto 0);
              interrupt : in std_logic;
                  reset : in std_logic;
                    clk : in std_logic);
    end component;
--
-- declaration of program ROM
--
  component int_test 
    Port (      address : in std_logic_vector(9 downto 0);
            instruction : out std_logic_vector(17 downto 0);
                    clk : in std_logic);
    end component;
--
------------------------------------------------------------------------------------
--
-- Signals used to connect KCPSM-II to program ROM and I/O logic
--
signal address : std_logic_vector(9 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal reset : std_logic;
--
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
begin

  -- Inserting KCPSM-II and the program memory

  processor: kcpsm2
    port map(      address => address,
               instruction => instruction,
                   port_id => port_id,
              write_strobe => write_strobe,
                  out_port => out_port,
               read_strobe => read_strobe,
                   in_port => in_port,
                 interrupt => interrupt_event,
                     reset => reset,
                       clk => clk);
 
  program: int_test
    port map(      address => address,
               instruction => instruction,
                       clk => clk);

  -- Unused inputs on processor

  in_port <= "00000000";
  reset <= '0';

  -- adding the output registers to the processor
   
  IO_registers: process(clk)
  begin

    -- waveform register at address 02

    if clk'event and clk='1' then
      if port_id(1)='1' and write_strobe='1' then
        waveforms <= out_port;
      end if;
    end if; 

    -- Interrupt Counter register at address 04

    if clk'event and clk='1' then
      if port_id(2)='1' and write_strobe='1' then
        counter <= out_port;
      end if;
    end if;
 
  end process IO_registers;

end Behavioral;

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--
-- END OF FILE KCPSM2_INT_TEST.VHD
--
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