📄 kcpsm2.vhd
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value_select_mux: mux2_LUT
port map( D1 => load_1_value(i),
D0 => load_0_value(i),
sel => select_load_value,
Y => selected_load_value(i));
count_select_mux: mux2_LUT
port map( D1 => count_value(i),
D0 => inc_load_value(i),
sel => normal_count,
Y => selected_count_value(i));
register_bit: FDRSE
port map ( D => inc_count_value(i),
Q => count_value(i),
R => reset,
S => force_3FF,
CE => not_enable,
C => clk);
lsb_carry: if i=0 generate
begin
load_inc_carry: MUXCY
port map( DI => '0',
CI => increment_load_value,
S => selected_load_value(i),
O => inc_load_value_carry(i));
load_inc_xor: XORCY
port map( LI => selected_load_value(i),
CI => increment_load_value,
O => inc_load_value(i));
count_inc_carry: MUXCY
port map( DI => '0',
CI => normal_count,
S => selected_count_value(i),
O => inc_count_value_carry(i));
count_inc_xor: XORCY
port map( LI => selected_count_value(i),
CI => normal_count,
O => inc_count_value(i));
end generate lsb_carry;
mid_carry: if i>0 and i<9 generate
begin
load_inc_carry: MUXCY
port map( DI => '0',
CI => inc_load_value_carry(i-1),
S => selected_load_value(i),
O => inc_load_value_carry(i));
load_inc_xor: XORCY
port map( LI => selected_load_value(i),
CI => inc_load_value_carry(i-1),
O => inc_load_value(i));
count_inc_carry: MUXCY
port map( DI => '0',
CI => inc_count_value_carry(i-1),
S => selected_count_value(i),
O => inc_count_value_carry(i));
count_inc_xor: XORCY
port map( LI => selected_count_value(i),
CI => inc_count_value_carry(i-1),
O => inc_count_value(i));
end generate mid_carry;
msb_carry: if i=9 generate
begin
load_inc_xor: XORCY
port map( LI => selected_load_value(i),
CI => inc_load_value_carry(i-1),
O => inc_load_value(i));
count_inc_xor: XORCY
port map( LI => selected_count_value(i),
CI => inc_count_value_carry(i-1),
O => inc_count_value(i));
end generate msb_carry;
end generate count_width_loop;
count <= count_value;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 10-bit program counter
--
-- This function provides the control to the dual loadable counter macro which uses
-- 3 LUTs. The total size of the program counter is then 23 LUTs (12 slices).
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity program_counter is
Port ( instruction17 : in std_logic;
instruction16 : in std_logic;
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction12 : in std_logic;
low_instruction : in std_logic_vector(9 downto 0);
stack_value : in std_logic_vector(9 downto 0);
flag_condition_met : in std_logic;
T_state : in std_logic;
reset : in std_logic;
force_3FF : in std_logic;
program_count : out std_logic_vector(9 downto 0);
clk : in std_logic);
end program_counter;
--
architecture low_level_definition of program_counter is
--
-- Definition of a 10-bit dual loadable counter
--
component dual_loadable_counter
Port ( load_1_value : in std_logic_vector(9 downto 0);
load_0_value : in std_logic_vector(9 downto 0);
select_load_value : in std_logic;
increment_load_value : in std_logic;
normal_count : in std_logic;
enable_bar : in std_logic;
reset : in std_logic;
force_3FF : in std_logic;
count : out std_logic_vector(9 downto 0);
clk : in std_logic);
end component;
--
-- Internal signals
--
signal move_group : std_logic;
signal normal_count : std_logic;
signal increment_vector : std_logic;
--
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of move_group_lut : label is "2A00";
attribute INIT of inc_vector_lut : label is "1";
attribute INIT of normal_count_lut : label is "2F";
--
begin
move_group_lut: LUT4
--translate_off
generic map (INIT => X"2A00")
--translate_on
port map( I0 => instruction14,
I1 => instruction15,
I2 => instruction16,
I3 => instruction17,
O => move_group );
normal_count_lut: LUT3
--translate_off
generic map (INIT => X"2F")
--translate_on
port map( I0 => instruction12,
I1 => flag_condition_met,
I2 => move_group,
O => normal_count );
inc_vector_lut: LUT2
--translate_off
generic map (INIT => X"1")
--translate_on
port map( I0 => instruction15,
I1 => instruction16,
O => increment_vector );
the_counter: dual_loadable_counter
port map ( load_1_value => low_instruction,
load_0_value => stack_value,
select_load_value => instruction16,
increment_load_value => increment_vector,
normal_count => normal_count,
enable_bar => T_state,
reset => reset,
force_3FF => force_3FF,
count => program_count,
clk => clk );
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Decode of flag conditions
--
-- This function determines if the flags meet the conditions specified in a
-- JUMP, CALL, or RETURN instruction. It is defined as a separate macro because
-- it provides information required by both the program counter and stack pointer.
--
-- It uses 1 LUT.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity flag_test is
Port ( instruction11 : in std_logic;
instruction10 : in std_logic;
zero_flag : in std_logic;
carry_flag : in std_logic;
condition_met : out std_logic );
end flag_test;
--
architecture low_level_definition of flag_test is
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of decode_lut : label is "5A3C";
--
begin
decode_lut: LUT4
--translate_off
generic map (INIT => X"5A3C")
--translate_on
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction10,
I3 => instruction11,
O => condition_met );
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of the Input and Output Strobes
--
-- Uses 3 LUTs and 2 FDR.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity IO_strobe_logic is
Port ( instruction17 : in std_logic;
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
active_interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
write_strobe : out std_logic;
read_strobe : out std_logic;
clk : in std_logic);
end IO_strobe_logic;
--
architecture low_level_definition of IO_strobe_logic is
--
-- Internal signals
--
signal IO_type : std_logic;
signal write_event : std_logic;
signal read_event : std_logic;
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of IO_type_lut : label is "10";
attribute INIT of write_lut : label is "1000";
attribute INIT of read_lut : label is "0100";
--
begin
--
IO_type_lut: LUT3
--translate_off
generic map (INIT => X"10")
--translate_on
port map( I0 => instruction14,
I1 => instruction15,
I2 => instruction17,
O => IO_type );
write_lut: LUT4
--translate_off
generic map (INIT => X"1000")
--translate_on
port map( I0 => active_interrupt,
I1 => T_state,
I2 => instruction13,
I3 => IO_type,
O => write_event );
write_flop: FDR
port map ( D => write_event,
Q => write_strobe,
R => reset,
C => clk);
read_lut: LUT4
--translate_off
generic map (INIT => X"0100")
--translate_on
port map( I0 => active_interrupt,
I1 => T_state,
I2 => instruction13,
I3 => IO_type,
O => read_event );
read_flop: FDR
port map ( D => read_event,
Q => read_strobe,
R => reset,
C => clk);
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of RAM for stack
--
-- This is a 32 location single port RAM of 10-bits to support the address range
-- of the program counter. The ouput is registered and the write enable is active low.
--
-- Ecah bit requires 1 slice, and therefore the 10-bit RAM requires 10-slices.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity stack_ram is
Port ( Din : in std_logic_vector(9 downto 0);
Dout : out std_logic_vector(9 downto 0);
addr : in std_logic_vector(4 downto 0);
write_bar : in std_logic;
clk : in std_logic);
end stack_ram;
--
architecture low_level_definition of stack_ram is
--
-- Internal signals
--
signal ram_out : std_logic_vector(9 downto 0);
signal write_enable : std_logic;
--
begin
invert_enable: INV -- Inverter should be implemented in the WE to RAM
port map( I => write_bar,
O => write_enable);
bus_width_loop: for i in 0 to 9 generate
--
-- Attribute to define RAM contents during implementation
-- The information is repeated in the generic map for functional simulation
--
attribute INIT : string;
attribute INIT of stack_ram_bit : label is "00000000";
--
begin
stack_ram_bit: RAM32X1S
-- translate_off
generic map(INIT => X"00000000")
-- translate_on
port map ( D => Din(i),
WE => write_enable,
WCLK => clk,
A0 => addr(0),
A1 => addr(1),
A2 => addr(2),
A3 => addr(3),
A4 => addr(4),
O => ram_out(i));
stack_ram_flop: FD
port map ( D => ram_out(i),
Q => Dout(i),
C => clk);
end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of a 5-bit special counter for stack pointer
--
-- This 5-bit counter is a relatively complex function
--
-- The counter is able to increment and decrement.
-- It can also hold current value during an active interrupt
-- and decrement by two during a RETURN or RETURNI.
--
-- Counter 5 LUTs, 5 FDREs, and associated carry logic.
-- Decoding lgic requires a futher 3 LUTs.
-- Total size 4 slices.
--
library IEEE;
use IEEE.S⌨️ 快捷键说明
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