kcpsm2.vhd

Xillinx 的8位MCU软核的源代码

entity register_and_flag_enable is
    Port (      instruction : in std_logic_vector(17 downto 13);
       	  active_interrupt : in std_logic;
                    T_state : in std_logic;
			   register_enable : out std_logic;
			       flag_enable : out std_logic;
			               clk : in std_logic);
    end register_and_flag_enable;
--
architecture low_level_definition of register_and_flag_enable is
--
-- Internal signals
--
signal reg_instruction_decode : std_logic;
signal register_write_valid : std_logic;
signal returni_or_shift_decode : std_logic;
signal returni_or_shift_valid : std_logic;
signal arith_or_logical_decode : std_logic;
signal arith_or_logical_valid : std_logic;
--
--
-- Attributes to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of reg_decode_lut : label is "0155"; 
attribute INIT of reg_pulse_timing_lut : label is "8"; 
attribute INIT of flag_decode1_lut : label is "00FE"; 
attribute INIT of flag_decode2_lut : label is "20";
attribute INIT of flag_pulse_timing_lut : label is "A8"; 
--
begin
  --
  -- Register enable
  --
  reg_decode_lut: LUT4
  --translate_off
    generic map (INIT => X"0155")
  --translate_on
  port map( I0 => active_interrupt,
            I1 => instruction(13),
            I2 => instruction(14),
            I3 => instruction(17),
             O => reg_instruction_decode );

  reg_pipeline_bit: FD
  port map ( D => reg_instruction_decode,
             Q => register_write_valid,
             C => clk);

  reg_pulse_timing_lut: LUT2
  --translate_off
    generic map (INIT => X"8")
  --translate_on
  port map( I0 => T_state,
            I1 => register_write_valid,
             O => register_enable );
  --
  -- Flag enable
  --
  flag_decode1_lut: LUT4
  --translate_off
    generic map (INIT => X"00FE")
  --translate_on
  port map( I0 => instruction(13),
            I1 => instruction(14),
            I2 => instruction(15),
            I3 => instruction(17),
             O => arith_or_logical_decode );

  flag_pipeline1_bit: FD
  port map ( D => arith_or_logical_decode,
             Q => arith_or_logical_valid,
             C => clk);

  flag_decode2_lut: LUT3
  --translate_off
    generic map (INIT => X"20")
  --translate_on
  port map( I0 => instruction(15),
            I1 => instruction(16),
            I2 => instruction(17),
             O => returni_or_shift_decode );

  flag_pipeline2_bit: FD
  port map ( D => returni_or_shift_decode,
             Q => returni_or_shift_valid,
             C => clk);

  flag_pulse_timing_lut: LUT3
  --translate_off
    generic map (INIT => X"A8")
  --translate_on
  port map( I0 => T_state,
            I1 => arith_or_logical_valid,
            I2 => returni_or_shift_valid,
             O => flag_enable );
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of basic time T-state and clean reset
--	
-- This function forms the basic 2 cycle T-state control used by the processor.
-- It also forms a clean synchronous reset pulse that is long enough to ensure 
-- correct operation at start up and following a reset input.
-- It uses 1 LUT, an FDR, and 2 FDS pimatives.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity T_state_and_Reset is
    Port (    reset_input : in std_logic;
       	  internal_reset : out std_logic;
                  T_state : out std_logic;
			             clk : in std_logic);
    end T_state_and_Reset;
--
architecture low_level_definition of T_state_and_Reset is
--
-- Internal signals
--
signal reset_delay1 : std_logic;
signal reset_delay2 : std_logic;
signal not_T_state : std_logic;
signal internal_T_state : std_logic;
--
--
-- Attributes to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of invert_lut : label is "1"; 
--
begin
  --
  delay_flop1: FDS
  port map ( D => '0',
             Q => reset_delay1,
             S => reset_input,
				 C => clk);

  delay_flop2: FDS
  port map ( D => reset_delay1,
             Q => reset_delay2,
             S => reset_input,
				 C => clk);
    
  invert_lut: LUT1
  --translate_off
    generic map (INIT => X"1")
  --translate_on
  port map( I0 => internal_T_state,
             O => not_T_state );

  toggle_flop: FDR
  port map ( D => not_T_state,
             Q => internal_T_state,
             R => reset_delay2,
				 C => clk);

  T_state <= internal_T_state;
  internal_reset <= reset_delay2;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of the Zero Flag 
--	
-- The ZERO value is detected using 2 LUTs and associated carry logic to 
-- form a wired NOR gate. A further LUT selects the source for the ZERO flag
-- which is stored in an FDRE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity zero_flag_logic is
    Port (          data : in std_logic_vector(7 downto 0);
       	  instruction17 : in std_logic;
       	  instruction14 : in std_logic;
			    shadow_zero : in std_logic;
                   reset : in std_logic;
             flag_enable : in std_logic;
               zero_flag : out std_logic;
                     clk : in std_logic);
    end zero_flag_logic;
--
architecture low_level_definition of zero_flag_logic is
--
-- Internal signals
--
signal lower_zero : std_logic;
signal upper_zero : std_logic;
signal lower_zero_carry : std_logic;
signal data_zero : std_logic;
signal next_zero_flag : std_logic;
--
--
-- Attributes to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of lower_zero_lut : label is "0001"; 
attribute INIT of upper_zero_lut : label is "0001"; 
attribute INIT of select_lut : label is "F870"; 
--
begin
  --
  -- Detect all bits in data are zero using wired NOR gate
  --
  lower_zero_lut: LUT4
  --translate_off
    generic map (INIT => X"0001")
  --translate_on
  port map( I0 => data(0),
            I1 => data(1),
            I2 => data(2),
            I3 => data(3),
             O => lower_zero );

  upper_zero_lut: LUT4
  --translate_off
    generic map (INIT => X"0001")
  --translate_on
  port map( I0 => data(4),
            I1 => data(5),
            I2 => data(6),
            I3 => data(7),
             O => upper_zero );

   lower_carry: MUXCY
   port map( DI => '0',
             CI => '1',
              S => lower_zero,
              O => lower_zero_carry );

	upper_carry: MUXCY
   port map( DI => '0',
             CI => lower_zero_carry,
              S => upper_zero,
              O => data_zero );
  --
  -- Select new zero status or the shaddow flag for a RETURNI
  --
  select_lut: LUT4
  --translate_off
    generic map (INIT => X"F870")
  --translate_on
  port map( I0 => instruction14,
            I1 => instruction17,
            I2 => data_zero,
            I3 => shadow_zero,
             O => next_zero_flag );

  zero_flag_flop: FDRE
  port map ( D => next_zero_flag,
             Q => zero_flag,
            CE => flag_enable,
             R => reset,
				 C => clk);
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of the Carry Flag 
--
-- 2 LUTs are used to select the source for the CARRY flag
-- which is stored in an FDRE.
--	
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity carry_flag_logic is
    Port ( instruction17 : in std_logic;
       	  instruction15 : in std_logic;
       	  instruction14 : in std_logic;
			    shift_carry : in std_logic;
			  add_sub_carry : in std_logic;
			   shadow_carry : in std_logic;
                   reset : in std_logic;
             flag_enable : in std_logic;
              carry_flag : out std_logic;
                     clk : in std_logic);
    end carry_flag_logic;
--
architecture low_level_definition of carry_flag_logic is
--
-- Internal signals
--
signal carry_status : std_logic;
signal next_carry_flag : std_logic;
--
--
-- Attributes to define LUT contents during implementation 
-- The information is repeated in the generic map for functional simulation
attribute INIT : string; 
attribute INIT of status_lut : label is "EC20"; 
attribute INIT of select_lut : label is "F870"; 
--
begin
  --
  status_lut: LUT4
  --translate_off
    generic map (INIT => X"EC20")
  --translate_on
  port map( I0 => instruction15,
            I1 => instruction17,
            I2 => add_sub_carry,
            I3 => shift_carry,
             O => carry_status );
  --
  -- Select new carry status or the shaddow flag for a RETURNI
  --
  select_lut: LUT4
  --translate_off
    generic map (INIT => X"F870")
  --translate_on
  port map( I0 => instruction14,
            I1 => instruction17,
            I2 => carry_status,
            I3 => shadow_carry,
             O => next_carry_flag );

  carry_flag_flop: FDRE
  port map ( D => next_carry_flag,
             Q => carry_flag,
            CE => flag_enable,
             R => reset,
				 C => clk);
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of a 10-bit dual loadable counter for use as Program Counter
--	
-- This function uses 20 LUTs and associated MUXCY/XORCY components.
-- The count value is held in 10 FDs.
--
-- Operation
--
-- When the normal_count signal is high the 10-bit counter will simply increment
-- by selecting the feedback from the register and incrementing it.
--
-- When the normal_count signal is low, the counter will load a new input value.
-- The new value can be selected from one of two inputs, and optionally incremented
-- before being applied to the counter register. 
--
-- In this way the counter can load an absolute value used during a JUMP or CALL,
-- instruction, or alternatively, load a value from the stack during a RETURN or 
-- RETURNI instruction. During a RETURN, the value must be incremented.
--
-- The register has an active low clock enable and a reset. 
-- It also has the ability to be forced to maximum count (3FF) in the event of an interrupt.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity dual_loadable_counter is
    Port (         load_1_value : in std_logic_vector(9 downto 0);
                   load_0_value : in std_logic_vector(9 downto 0);
              select_load_value : in std_logic;
		     increment_load_value : in std_logic;
			          normal_count : in std_logic;
			            enable_bar : in std_logic;
			                 reset : in std_logic;
			             force_3FF : in std_logic;
					           count : out std_logic_vector(9 downto 0);
			                   clk : in std_logic);
    end dual_loadable_counter;
--
architecture low_level_definition of dual_loadable_counter is
--	
-- A 2 to 1 multiplexer in a LUT
--
component mux2_LUT is
    Port (  D1 : in std_logic;
            D0 : in std_logic;
           sel : in std_logic;
             Y : out std_logic);
    end component;
--
-- Internal signals
--
signal not_enable : std_logic;
--
signal selected_load_value : std_logic_vector(9 downto 0);
signal inc_load_value_carry : std_logic_vector(8 downto 0);
signal inc_load_value : std_logic_vector(9 downto 0);
--
signal selected_count_value : std_logic_vector(9 downto 0);
signal inc_count_value_carry : std_logic_vector(8 downto 0);
signal inc_count_value : std_logic_vector(9 downto 0);
--
signal count_value : std_logic_vector(9 downto 0);
--
begin

  invert_enable: INV   -- Inverter should be implemented in the CE to flip flops
  port map(  I => enable_bar,
             O => not_enable);  
 
  count_width_loop: for i in 0 to 9 generate

  begin