📄 kcpsm2.vhd
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clk : in std_logic);
end logical_bus_processing;
--
architecture low_level_definition of logical_bus_processing is
--
-- Internal signals
--
signal combinatorial_logical_processing : std_logic_vector(7 downto 0);
--
begin
bus_width_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of logical_lut : label is "6E8A";
--
begin
logical_lut: LUT4
--translate_off
generic map (INIT => X"6E8A")
--translate_on
port map( I0 => second_operand(i),
I1 => first_operand(i),
I2 => code0,
I3 => code1,
O => combinatorial_logical_processing(i));
pipeline_bit: FD
port map ( D => combinatorial_logical_processing(i),
Q => Y(i),
C => clk);
end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit adder/subtractor
--
-- This function uses 8 LUTs and associated MUXCY/XORCY components.
-- The function contains an output pipeline register using 8 FDs.
-- Total size is 4 slices.
--
-- subtract Operation
--
-- 0 ADD Y <= first_operand + second_operand
-- 1 SUB Y <= first_operand - second_operand
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity addsub8 is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
subtract : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end addsub8;
--
architecture low_level_definition of addsub8 is
--
-- Internal signals
--
signal half_addsub : std_logic_vector(7 downto 0);
signal full_addsub : std_logic_vector(7 downto 0);
signal carry_chain : std_logic_vector(6 downto 0);
--
begin
bus_width_loop: for i in 0 to 7 generate
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of arithmetic_lut : label is "96";
--
begin
lsb_carry: if i=0 generate
begin
arithmetic_carry: MUXCY
port map( DI => first_operand(i),
CI => carry_in,
S => half_addsub(i),
O => carry_chain(i));
arithmetic_xor: XORCY
port map( LI => half_addsub(i),
CI => carry_in,
O => full_addsub(i));
end generate lsb_carry;
mid_carry: if i>0 and i<7 generate
begin
arithmetic_carry: MUXCY
port map( DI => first_operand(i),
CI => carry_chain(i-1),
S => half_addsub(i),
O => carry_chain(i));
arithmetic_xor: XORCY
port map( LI => half_addsub(i),
CI => carry_chain(i-1),
O => full_addsub(i));
end generate mid_carry;
msb_carry: if i=7 generate
begin
arithmetic_carry: MUXCY
port map( DI => first_operand(i),
CI => carry_chain(i-1),
S => half_addsub(i),
O => carry_out);
arithmetic_xor: XORCY
port map( LI => half_addsub(i),
CI => carry_chain(i-1),
O => full_addsub(i));
end generate msb_carry;
arithmetic_lut: LUT3
--translate_off
generic map (INIT => X"96")
--translate_on
port map( I0 => first_operand(i),
I1 => second_operand(i),
I2 => subtract,
O => half_addsub(i));
pipeline_bit: FD
port map ( D => full_addsub(i),
Q => Y(i),
C => clk);
end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit shift/rotate process
--
-- This function uses 11 LUTs.
-- The function contains an output pipeline register using 9 FDs.
--
-- Operation
--
-- The input operand is shifted by one bit left or right.
-- The bit which falls out of the end is passed to the carry_out.
-- The bit shifted in is determined by the select bits
--
-- code1 code0 Bit injected
--
-- 0 0 carry_in
-- 0 1 msb of input_operand
-- 1 0 lsb of operand
-- 1 1 inject_bit
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity shift_rotate_process is
Port ( operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
inject_bit : in std_logic;
shift_right : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end shift_rotate_process;
--
architecture low_level_definition of shift_rotate_process is
--
-- A 2 to 1 multiplexer in a LUT
--
component mux2_LUT
Port ( D1 : in std_logic;
D0 : in std_logic;
sel : in std_logic;
Y : out std_logic);
end component;
--
-- A 4 to 1 multiplexer using 2 LUTs and an MUXF5
--
component mux4_LUTS_MUXF5
Port ( D3 : in std_logic;
D2 : in std_logic;
D1 : in std_logic;
D0 : in std_logic;
sel1 : in std_logic;
sel0 : in std_logic;
Y : out std_logic);
end component;
--
-- Internal signals
--
signal mux_output : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
signal carry_bit : std_logic;
--
begin
--
-- Selection of the bit to be shifted in
--
input_bit_mux4: mux4_LUTS_MUXF5
port map( D3 => inject_bit,
D2 => operand(0),
D1 => operand(7),
D0 => carry_in,
sel1 => code1,
sel0 => code0,
Y => shift_in_bit);
--
-- shift left or right of operand
--
bus_width_loop: for i in 0 to 7 generate
--
begin
lsb_shift: if i=0 generate
begin
bit_mux2: mux2_LUT
port map( D1 => operand(i+1),
D0 => shift_in_bit,
sel => shift_right,
Y => mux_output(i));
end generate lsb_shift;
mid_shift: if i>0 and i<7 generate
begin
bit_mux2: mux2_LUT
port map( D1 => operand(i+1),
D0 => operand(i-1),
sel => shift_right,
Y => mux_output(i));
end generate mid_shift;
msb_shift: if i=7 generate
begin
bit_mux2: mux2_LUT
port map( D1 => shift_in_bit,
D0 => operand(i-1),
sel => shift_right,
Y => mux_output(i));
end generate msb_shift;
pipeline_bit: FD
port map ( D => mux_output(i),
Q => Y(i),
C => clk);
end generate bus_width_loop;
--
-- Selection of carry output
--
carry_out_mux2: mux2_LUT
port map( D1 => operand(0),
D0 => operand(7),
sel => shift_right,
Y => carry_bit);
pipeline_bit: FD
port map ( D => carry_bit,
Q => carry_out,
C => clk);
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit arithmetic process
--
-- This function uses 10 LUTs and associated carry logic.
-- The function contains an output pipeline register using 9 FDs.
--
-- Operation
--
-- Two input operands are added or subtracted.
-- An input carry bit can be included in the calculation.
-- An output carry is always generated.
-- Carry signals work in the positive sense at all times.
--
-- code1 code0 Bit injected
--
-- 0 0 ADD
-- 0 1 ADD with carry
-- 1 0 SUB
-- 1 1 SUB with carry
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity arithmetic_process is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end arithmetic_process;
--
architecture low_level_definition of arithmetic_process is
--
-- An 8-bit adder/subtractor
--
component addsub8
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
subtract : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
--
-- Internal signals
--
signal carry_in_bit : std_logic;
signal carry_out_bit : std_logic;
signal modified_carry_out : std_logic;
--
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of carry_input_lut : label is "78";
attribute INIT of carry_output_lut : label is "6";
--
begin
--
-- Selection of the carry input to add/sub
--
carry_input_lut: LUT3
--translate_off
generic map (INIT => X"78")
--translate_on
port map( I0 => carry_in,
I1 => code0,
I2 => code1,
O => carry_in_bit );
--
-- Main add/sub
--
add_sub_module: addsub8
port map ( first_operand => first_operand,
second_operand => second_operand,
carry_in => carry_in_bit,
subtract => code1,
Y => Y,
carry_out => carry_out_bit,
clk => clk);
--
-- Modification to carry output and pipeline
--
carry_output_lut: LUT2
--translate_off
generic map (INIT => X"6")
--translate_on
port map( I0 => carry_out_bit,
I1 => code1,
O => modified_carry_out );
pipeline_bit: FD
port map ( D => modified_carry_out,
Q => carry_out,
C => clk);
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of write enable for register bank and flags
--
-- This function decodes all instructions which result in a value being stored
-- in the data registers and those cases in which the flags must be enabled.
-- It uses 5 LUTs and and 3 FDs.
-- The generation of a register enable pulse is prevented by an active interrupt condition.
-- The single cycle pulse timing of each enable is determined by the T-state.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
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