📄 kcpsm2.vhd
字号:
Y_bus => second_operand);
--
-- The ALU structure
--
logical_group: logical_bus_processing
port map ( first_operand => sX_register,
second_operand => second_operand,
code1 => instruction(14),
code0 => instruction(13),
Y => logical_result,
clk => clk);
arithmetic_group: arithmetic_process
port map ( first_operand => sX_register,
second_operand => second_operand,
carry_in => carry_flag,
code1 => instruction(14),
code0 => instruction(13),
Y => arithmetic_result,
carry_out => arithmetic_carry,
clk => clk);
shift_group: shift_rotate_process
port map ( operand => sX_register,
carry_in => carry_flag,
inject_bit => instruction(0),
shift_right => instruction(3),
code1 => instruction(2),
code0 => instruction(1),
Y => shift_and_rotate_result,
carry_out => shift_and_rotate_carry,
clk => clk);
ALU_mux: data_bus_mux4
port map ( D3_bus => shift_and_rotate_result,
D2_bus => in_port,
D1_bus => arithmetic_result,
D0_bus => logical_result,
sel1 => instruction(17),
sel0 => instruction(15),
Y_bus => ALU_result);
--
-- Program Counter
--
prog_count: program_counter
port map ( instruction17 => instruction(17),
instruction16 => instruction(16),
instruction15 => instruction(15),
instruction14 => instruction(14),
instruction12 => instruction(12),
low_instruction => instruction(9 downto 0),
stack_value => stack_pop_data,
flag_condition_met => flag_condition_met,
T_state => T_state,
reset => internal_reset,
force_3FF => active_interrupt,
program_count => program_count,
clk => clk );
address <= program_count;
--
-- Program stack
--
stack_memory: stack_ram
port map ( Din => program_count,
Dout => stack_pop_data,
addr => stack_pointer,
write_bar => T_state,
clk => clk );
stack_control: stack_counter
port map ( instruction17 => instruction(17),
instruction16 => instruction(16),
instruction14 => instruction(14),
instruction13 => instruction(13),
instruction12 => instruction(12),
T_state => T_state,
flag_condition_met => flag_condition_met,
active_interrupt => active_interrupt,
reset => internal_reset,
stack_count => stack_pointer,
clk => clk );
--
-- Input and Output Strobes
--
IO_strobes: IO_strobe_logic
port map ( instruction17 => instruction(17),
instruction15 => instruction(15),
instruction14 => instruction(14),
instruction13 => instruction(13),
active_interrupt => active_interrupt,
T_state => T_state,
reset => internal_reset,
write_strobe => write_strobe,
read_strobe => read_strobe,
clk => clk );
--
-- Capture of interrupt signal
--
get_interrupt: interrupt_capture
port map ( interrupt => interrupt,
T_state => T_state,
reset => internal_reset,
interrupt_enable => interrupt_enable,
active_interrupt => active_interrupt,
clk => clk );
--
-- Interrupt Enable and shaddow flags
--
interrupt_control: interrupt_logic
port map ( instruction17 => instruction(17),
instruction15 => instruction(15),
instruction14 => instruction(14),
instruction0 => instruction(0),
active_interrupt => active_interrupt,
carry_flag => carry_flag,
zero_flag => zero_flag,
reset => internal_reset,
interrupt_enable => interrupt_enable,
shaddow_carry => shaddow_carry_flag,
shaddow_zero => shaddow_zero_flag,
clk => clk );
--
end macro_level_definition;
--
------------------------------------------------------------------------------------
--
-- End of top level description for KCPSM2.
--
------------------------------------------------------------------------------------
--
-- Description of sub-modules and further low level modules.
--
------------------------------------------------------------------------------------
--
-- Definition of a 2 to 1 multiplexer in a LUT
--
-- This simple function is used many times.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity mux2_LUT is
Port ( D1 : in std_logic;
D0 : in std_logic;
sel : in std_logic;
Y : out std_logic);
end mux2_LUT;
--
architecture low_level_definition of mux2_LUT is
--
-- Attribute to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of the_mux_lut : label is "E4";
--
begin
the_mux_lut: LUT3
--translate_off
generic map (INIT => X"E4")
--translate_on
port map( I0 => sel,
I1 => D0,
I2 => D1,
O => Y );
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of a 4 to 1 multiplexer using 2 LUTs and an MUXF5
--
-- Builds on the definition of a 2 to 1 multiplexer on a LUT to
-- create a 4 to 1 multiplexer in a 'slice'.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity mux4_LUTS_MUXF5 is
Port ( D3 : in std_logic;
D2 : in std_logic;
D1 : in std_logic;
D0 : in std_logic;
sel1 : in std_logic;
sel0 : in std_logic;
Y : out std_logic);
end mux4_LUTS_MUXF5;
--
architecture low_level_definition of mux4_LUTS_MUXF5 is
--
--
-- A 2 to 1 multiplexer in a LUT
--
component mux2_LUT is
Port ( D1 : in std_logic;
D0 : in std_logic;
sel : in std_logic;
Y : out std_logic);
end component;
--
-- Internal signals
--
signal upper_selection : std_logic;
signal lower_selection : std_logic;
--
begin
upper_mux: mux2_LUT
port map( D1 => D3,
D0 => D2,
sel => sel0,
Y => upper_selection );
lower_mux: mux2_LUT
port map( D1 => D1,
D0 => D0,
sel => sel0,
Y => lower_selection );
final_mux: MUXF5
port map( I1 => upper_selection,
I0 => lower_selection,
S => sel1,
O => Y );
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit bus 2 to 1 multiplexer
--
-- Requires 8 LUTs or 4 'slices'.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity data_bus_mux2 is
Port ( D1_bus : in std_logic_vector(7 downto 0);
D0_bus : in std_logic_vector(7 downto 0);
sel : in std_logic;
Y_bus : out std_logic_vector(7 downto 0));
end data_bus_mux2;
--
architecture macro_level_definition of data_bus_mux2 is
--
-- A 2 to 1 multiplexer in a LUT
--
component mux2_LUT is
Port ( D1 : in std_logic;
D0 : in std_logic;
sel : in std_logic;
Y : out std_logic);
end component;
--
begin
bus_width_loop: for i in 0 to 7 generate
begin
bit_mux2: mux2_LUT
port map( D1 => D1_bus(i),
D0 => D0_bus(i),
sel => sel,
Y => Y_bus(i));
end generate bus_width_loop;
--
end macro_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit bus 4 to 1 multiplexer
--
-- Requires 8 'slices'.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
entity data_bus_mux4 is
Port ( D3_bus : in std_logic_vector(7 downto 0);
D2_bus : in std_logic_vector(7 downto 0);
D1_bus : in std_logic_vector(7 downto 0);
D0_bus : in std_logic_vector(7 downto 0);
sel1 : in std_logic;
sel0 : in std_logic;
Y_bus : out std_logic_vector(7 downto 0));
end data_bus_mux4;
--
architecture macro_level_definition of data_bus_mux4 is
--
-- A 4 to 1 multiplexer using 2 LUTs and an MUXF5 (1 slice)
--
component mux4_LUTS_MUXF5 is
Port ( D3 : in std_logic;
D2 : in std_logic;
D1 : in std_logic;
D0 : in std_logic;
sel1 : in std_logic;
sel0 : in std_logic;
Y : out std_logic);
end component;
--
begin
bus_width_loop: for i in 0 to 7 generate
begin
bit_mux4: mux4_LUTS_MUXF5
port map( D3 => D3_bus(i),
D2 => D2_bus(i),
D1 => D1_bus(i),
D0 => D0_bus(i),
sel1 => sel1,
sel0 => sel0,
Y => Y_bus(i));
end generate bus_width_loop;
--
end macro_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit dual port RAM with 32 locations
--
-- This mode of distributed RAM requires 2 'slices' per bit.
-- Hence this 8-bit module requires 16 'slices'.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity data_register_bank is
Port ( Address_A : in std_logic_vector(4 downto 0);
Din_A_bus : in std_logic_vector(7 downto 0);
Write_A_bus : in std_logic;
Dout_A_bus : out std_logic_vector(7 downto 0);
Address_B : in std_logic_vector(4 downto 0);
Dout_B_bus : out std_logic_vector(7 downto 0);
clk : in std_logic);
end data_register_bank;
--
architecture low_level_definition of data_register_bank is
--
begin
bus_width_loop: for i in 0 to 7 generate
--
-- Attribute to define RAM contents during implementation
-- The information is repeated in the generic map for functional simulation
attribute INIT : string;
attribute INIT of data_register_bit : label is "00000000";
--
begin
data_register_bit: RAM32X1D
-- translate_off
generic map(INIT => X"00000000")
-- translate_on
port map ( D => Din_A_bus(i),
WE => Write_A_bus,
WCLK => clk,
A0 => Address_A(0),
A1 => Address_A(1),
A2 => Address_A(2),
A3 => Address_A(3),
A4 => Address_A(4),
DPRA0 => Address_B(0),
DPRA1 => Address_B(1),
DPRA2 => Address_B(2),
DPRA3 => Address_B(3),
DPRA4 => Address_B(4),
SPO => Dout_A_bus(i),
DPO => Dout_B_bus(i));
end generate bus_width_loop;
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- Definition of an 8-bit logical processing unit
--
-- This function uses 8 LUTs (4 slices) to provide the logical bit operations.
-- The function contains an output pipeline register using 8 FDs.
--
-- Code1 Code0 Bit Operation
--
-- 0 0 LOAD Y <= second_operand
-- 0 1 AND Y <= first_operand and second_operand
-- 1 0 OR Y <= first_operand or second_operand
-- 1 1 XOR Y <= first_operand xor second_operand
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
entity logical_bus_processing is
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -