📄 kcpsm2.vhd
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-- Constant (K) Coded Programmable State Machine for Virtex-II Devices
--
-- Version : 1.0
-- Version Date : 13th December 2001
--
-- Start of design entry : 15th October 2001
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2001. This code may be contain portions patented by other
-- third parites. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Throughout this file containing a collection of entities, the following libraries
-- are used.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
-- It is only specified in modules containing primitive components.
--
-- library unisim;
-- use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for KCPSM2
--
entity kcpsm2 is
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm2;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for KCPSM2
--
architecture macro_level_definition of kcpsm2 is
--
------------------------------------------------------------------------------------
--
-- Components used in KCPSM2 and defined in subsequent entities.
--
------------------------------------------------------------------------------------
--
-- An 8-bit bus 2 to 1 multiplexer
--
component data_bus_mux2
Port ( D1_bus : in std_logic_vector(7 downto 0);
D0_bus : in std_logic_vector(7 downto 0);
sel : in std_logic;
Y_bus : out std_logic_vector(7 downto 0));
end component;
--
-- An 8-bit bus 4 to 1 multiplexer
--
component data_bus_mux4
Port ( D3_bus : in std_logic_vector(7 downto 0);
D2_bus : in std_logic_vector(7 downto 0);
D1_bus : in std_logic_vector(7 downto 0);
D0_bus : in std_logic_vector(7 downto 0);
sel1 : in std_logic;
sel0 : in std_logic;
Y_bus : out std_logic_vector(7 downto 0));
end component;
--
-- An 8-bit dual port RAM
--
component data_register_bank
Port ( Address_A : in std_logic_vector(4 downto 0);
Din_A_bus : in std_logic_vector(7 downto 0);
Write_A_bus : in std_logic;
Dout_A_bus : out std_logic_vector(7 downto 0);
Address_B : in std_logic_vector(4 downto 0);
Dout_B_bus : out std_logic_vector(7 downto 0);
clk : in std_logic);
end component;
--
-- Definition of an 8-bit logical processing unit
--
component logical_bus_processing
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
clk : in std_logic);
end component;
--
-- Definition of an 8-bit shift/rotate process
--
component shift_rotate_process
Port ( operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
inject_bit : in std_logic;
shift_right : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
--
-- An 8-bit arithmetic process
--
component arithmetic_process
Port ( first_operand : in std_logic_vector(7 downto 0);
second_operand : in std_logic_vector(7 downto 0);
carry_in : in std_logic;
code1 : in std_logic;
code0 : in std_logic;
Y : out std_logic_vector(7 downto 0);
carry_out : out std_logic;
clk : in std_logic);
end component;
--
-- Decoding and timing of write enable for register bank and clock enable for flags
--
component register_and_flag_enable
Port ( instruction : in std_logic_vector(17 downto 13);
active_interrupt : in std_logic;
T_state : in std_logic;
register_enable : out std_logic;
flag_enable : out std_logic;
clk : in std_logic);
end component;
--
-- Reset conditioning and T-state generation
--
component T_state_and_Reset
Port ( reset_input : in std_logic;
internal_reset : out std_logic;
T_state : out std_logic;
clk : in std_logic);
end component;
--
-- Zero Flag logic
--
component zero_flag_logic
Port ( data : in std_logic_vector(7 downto 0);
instruction17 : in std_logic;
instruction14 : in std_logic;
shadow_zero : in std_logic;
reset : in std_logic;
flag_enable : in std_logic;
zero_flag : out std_logic;
clk : in std_logic);
end component;
--
-- Carry Flag logic
--
component carry_flag_logic
Port ( instruction17 : in std_logic;
instruction15 : in std_logic;
instruction14 : in std_logic;
shift_carry : in std_logic;
add_sub_carry : in std_logic;
shadow_carry : in std_logic;
reset : in std_logic;
flag_enable : in std_logic;
carry_flag : out std_logic;
clk : in std_logic);
end component;
--
-- Definition of a 10-bit Program Counter
--
component program_counter
Port ( instruction17 : in std_logic;
instruction16 : in std_logic;
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction12 : in std_logic;
low_instruction : in std_logic_vector(9 downto 0);
stack_value : in std_logic_vector(9 downto 0);
flag_condition_met : in std_logic;
T_state : in std_logic;
reset : in std_logic;
force_3FF : in std_logic;
program_count : out std_logic_vector(9 downto 0);
clk : in std_logic);
end component;
--
-- Decode of flag conditions
--
component flag_test
Port ( instruction11 : in std_logic;
instruction10 : in std_logic;
zero_flag : in std_logic;
carry_flag : in std_logic;
condition_met : out std_logic );
end component;
--
-- Input and Output Strobes
--
component IO_strobe_logic
Port ( instruction17 : in std_logic;
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
active_interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
write_strobe : out std_logic;
read_strobe : out std_logic;
clk : in std_logic);
end component;
--
-- RAM for program counter stack
--
component stack_ram
Port ( Din : in std_logic_vector(9 downto 0);
Dout : out std_logic_vector(9 downto 0);
addr : in std_logic_vector(4 downto 0);
write_bar : in std_logic;
clk : in std_logic);
end component;
--
-- Address pointer for program stack
--
component stack_counter is
Port ( instruction17 : in std_logic;
instruction16 : in std_logic;
instruction14 : in std_logic;
instruction13 : in std_logic;
instruction12 : in std_logic;
T_state : in std_logic;
flag_condition_met : in std_logic;
active_interrupt : in std_logic;
reset : in std_logic;
stack_count : out std_logic_vector(4 downto 0);
clk : in std_logic);
end component;
--
-- Capture of interrupt signal
--
component interrupt_capture is
Port ( interrupt : in std_logic;
T_state : in std_logic;
reset : in std_logic;
interrupt_enable : in std_logic;
active_interrupt : out std_logic;
clk : in std_logic);
end component;
--
-- Interrupt Enable and shaddow flags
--
component interrupt_logic is
Port ( instruction17 : in std_logic;
instruction15 : in std_logic;
instruction14 : in std_logic;
instruction0 : in std_logic;
active_interrupt : in std_logic;
carry_flag : in std_logic;
zero_flag : in std_logic;
reset : in std_logic;
interrupt_enable : out std_logic;
shaddow_carry : out std_logic;
shaddow_zero : out std_logic;
clk : in std_logic);
end component;
--
------------------------------------------------------------------------------------
--
-- Signals used in KCPSM
--
------------------------------------------------------------------------------------
--
-- Fundamental control signals
--
signal T_state : std_logic;
signal internal_reset : std_logic;
--
-- Register bank signals
--
signal sX_register : std_logic_vector(7 downto 0);
signal sY_register : std_logic_vector(7 downto 0);
signal register_write_enable : std_logic;
--
-- ALU signals
--
signal second_operand : std_logic_vector(7 downto 0);
signal logical_result : std_logic_vector(7 downto 0);
signal shift_and_rotate_result : std_logic_vector(7 downto 0);
signal shift_and_rotate_carry : std_logic;
signal arithmetic_result : std_logic_vector(7 downto 0);
signal arithmetic_carry : std_logic;
signal ALU_result : std_logic_vector(7 downto 0);
--
-- Flag signals
--
signal carry_flag : std_logic;
signal zero_flag : std_logic;
signal flag_clock_enable : std_logic;
signal flag_condition_met : std_logic;
--
-- Interrupt signals
--
signal shaddow_carry_flag : std_logic;
signal shaddow_zero_flag : std_logic;
signal interrupt_enable : std_logic;
signal active_interrupt : std_logic;
--
-- Program Counter and Stack signals
--
signal program_count : std_logic_vector(9 downto 0);
signal stack_pop_data : std_logic_vector(9 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
------------------------------------------------------------------------------------
--
-- Start of KCPSM2 circuit description
--
------------------------------------------------------------------------------------
--
begin
--
-- Connections to output port and port address
--
out_port <= sX_register;
port_id <= second_operand;
--
-- Reset conditioning and T-state generation
--
basic_control: T_state_and_Reset
port map ( reset_input => reset,
internal_reset => internal_reset,
T_state => T_state,
clk => clk);
--
-- Register bank and flags
--
data_registers: data_register_bank
port map ( Address_A => instruction(12 downto 8),
Din_A_bus => ALU_result,
Write_A_bus => register_write_enable,
Dout_A_bus => sX_register,
Address_B => instruction(7 downto 3),
Dout_B_bus => sY_register,
clk => clk);
zero: zero_flag_logic
port map ( data => ALU_result,
instruction17 => instruction(17),
instruction14 => instruction(14),
shadow_zero => shaddow_zero_flag,
reset => internal_reset,
flag_enable => flag_clock_enable,
zero_flag => zero_flag,
clk => clk);
carry: carry_flag_logic
port map ( instruction17 => instruction(17),
instruction15 => instruction(15),
instruction14 => instruction(14),
shift_carry => shift_and_rotate_carry,
add_sub_carry => arithmetic_carry,
shadow_carry => shaddow_carry_flag,
reset => internal_reset,
flag_enable => flag_clock_enable,
carry_flag => carry_flag,
clk => clk);
reg_and_flag_enables: register_and_flag_enable
port map ( instruction => instruction(17 downto 13),
active_interrupt => active_interrupt,
T_state => T_state,
register_enable => register_write_enable,
flag_enable => flag_clock_enable,
clk => clk);
--
-- Test of flags
--
test_flags: flag_test
port map ( instruction11 => instruction(11),
instruction10 => instruction(10),
zero_flag => zero_flag,
carry_flag => carry_flag,
condition_met => flag_condition_met );
--
-- Selection of second operand and port address
--
operand_select: data_bus_mux2
port map ( D1_bus => sY_register,
D0_bus => instruction(7 downto 0),
sel => instruction(16),
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