i2c_vpl_uc.v

用FPGA做主控制器

//-----------------------------------------------------------------
// i2c_vpl_uc.v
//
// I2C Video Peripheral Loader
//
//
//
//                  Author: Gregg C. Hawkes, Xilinx, Inc.
//                  Date:   Feb. 15, 2001
//                  For:    Xilinx Applications
//
//                  RESTRICTED RIGHTS LEGEND
//
//      This software has not been published by the author, and 
//      has been disclosed to others for the purpose of enhancing 
//      and promoting design productivity in Xilinx products.
//
//      Therefore use, duplication or disclosure, now and in the 
//      future should give consideration to the productivity 
//      enhancements afforded the user of this code by the author's 
//      efforts.
// 
// Revision:
//          February 15, 2001   Creation
//          September 6, 2001   Integrating more functions into KPCSM
//          xxx. xx, 2001       Clean up 
//
//
// Other modules instanced in this design:
//
//          KCPSM_V.EDN (Modified, removing verilog reserved words)
//          KCPSM_v_ROM (I2C code ROM output by KCPSM assembler)
//          RAMB4_S16_S16 (for data RAM)
//
//
/*

Disclaimer I2C is a registered trademark of Philips Electronics N.V..
Xilinx provides this reference design as one possible implementation of
the standard and claims no rights to this interface. Contact Philips to
obtain any necessary rights associated with this interface.
BRIEF DESCRIPTION

For most video peripheral chips, the I2C interface is used to load
initialization parameters. A complete I2C interface is really not needed
for this process. In fact, The intialization of the video functions can
be accomplished by a simple microcontroller and a RAM containing the
appropriate load values to be sent out to the video peripheral chips. 

Expansion to a full I2C interface will probably not require any verilog
changes. I will undertake this later, but my guess is that there will be
two main routines that will require the code to be written in a
multi-tasking method. The two tasks could be termed "Master", which is
written below, and "Slave". Multi-tasking between the two would be
accomplished by having the main calling routine execute one "state" from
the master, then one "state" from the slave, etc. 

Again, I believe these to be assembly language changes and should not
effect the verilog below.


DETAILED DESCRIPTION:

As mentioned above, the I2C interface will be supported (Master 
only) to facilitate the loading of video peripheral chips outside
of the FPGA.

A simple I2C interface description might be stated as:

Philips developed a simple bidirectional 2-wire bus for efficient
inter-IC control. This bus is called the Inter IC or I2C-bus. At
present, Philips