pc104_cpld.tan.qmsg

是关于对数据采集卡的基于PC104总线的读写程序

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "Clk ChannelVector\[0\] AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\] 5.000 ns register " "Info: Minimum tco from clock Clk to destination pin ChannelVector\[0\] through register AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\] is 5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 1.500 ns + Shortest register " "Info: + Shortest clock path from clock Clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk 1 CLK Pin_87 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = Pin_87; Fanout = 19; CLK Node = 'Clk'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 168 1080 1248 184 "Clk" "" } { 232 1280 1320 248 "Clk" "" } { 160 1280 1320 176 "Clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\] 2 REG LC29 6 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC29; Fanout = 6; REG Node = 'AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.000 ns" { Clk AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] } "NODE_NAME" } } } { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.500 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\] 1 REG LC29 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC29; Fanout = 6; REG Node = 'AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] } "NODE_NAME" } } } { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns ChannelVector\[0\] 2 PIN Pin_6 0 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = Pin_6; Fanout = 0; PIN Node = 'ChannelVector\[0\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] ChannelVector[0] } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 272 1584 1776 288 "ChannelVector\[3..0\]" "" } { 264 1520 1617 280 "ChannelVector\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 100.00 % " "Info: Total cell delay = 2.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] ChannelVector[0] } "NODE_NAME" } } }  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] ChannelVector[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SA\[8\] CS_D 8.000 ns Shortest " "Info: Shortest tpd from source pin SA\[8\] to destination pin CS_D is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SA\[8\] 1 PIN Pin_44 74 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_44; Fanout = 74; PIN Node = 'SA\[8\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { SA[8] } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 24 -96 72 40 "SA\[9..0\]" "" } { 16 72 136 32 "SA\[9..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 5.500 ns AddressDecoder:inst3\|i15~13 2 COMB LC33 1 " "Info: 2: + IC(1.000 ns) + CELL(4.000 ns) = 5.500 ns; Loc. = LC33; Fanout = 1; COMB Node = 'AddressDecoder:inst3\|i15~13'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "5.000 ns" { SA[8] AddressDecoder:inst3|i15~13 } "NODE_NAME" } } } { "e:/pc104_cpld/AddressDecoder.vhd" "" "" { Text "e:/pc104_cpld/AddressDecoder.vhd" 40 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 8.000 ns CS_D 3 PIN Pin_25 0 " "Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 8.000 ns; Loc. = Pin_25; Fanout = 0; PIN Node = 'CS_D'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AddressDecoder:inst3|i15~13 CS_D } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 184 376 552 200 "CS_D" "" } { 176 312 376 192 "CS_D" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 87.50 % " "Info: Total cell delay = 7.000 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 12.50 % " "Info: Total interconnect delay = 1.000 ns ( 12.50 % )" {  } {  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "8.000 ns" { SA[8] AddressDecoder:inst3|i15~13 CS_D } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 11 14:08:26 2006 " "Info: Processing ended: Thu May 11 14:08:26 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}