pc104_cpld.tan.qmsg

是关于对数据采集卡的基于PC104总线的读写程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "IOW " "Info: Assuming node IOW is an undefined clock" {  } { { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 224 -96 72 240 "IOW" "" } { 216 72 106 232 "IOW" "" } { 256 688 776 272 "IOW" "" } } } } { "d:/program files/quartus4.0/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/quartus4.0/bin/Assignment Editor.qase" 1 { { 0 "IOW" } } } }  } 0} { "Info" "ITDB_NODE_MAP_TO_CLK" "Clk " "Info: Assuming node Clk is an undefined clock" {  } { { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 168 1080 1248 184 "Clk" "" } { 232 1280 1320 248 "Clk" "" } { 160 1280 1320 176 "Clk" "" } } } } { "d:/program files/quartus4.0/bin/Assignment Editor.qase" "" "" { Assignment "d:/program files/quartus4.0/bin/Assignment Editor.qase" 1 { { 0 "Clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "IOW register RegAndIntMode:inst\|IOCtrlReg\[3\] register RegAndIntMode:inst\|IOCtrlReg\[3\] 125.0 MHz 8.0 ns Internal " "Info: Clock IOW has Internal fmax of 125.0 MHz between source register RegAndIntMode:inst\|IOCtrlReg\[3\] and destination register RegAndIntMode:inst\|IOCtrlReg\[3\] (period= 8.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register register " "Info: + Longest register to register delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RegAndIntMode:inst\|IOCtrlReg\[3\] 1 REG LC77 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC77; Fanout = 7; REG Node = 'RegAndIntMode:inst\|IOCtrlReg\[3\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns RegAndIntMode:inst\|IOCtrlReg\[3\] 2 REG LC77 7 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = LC77; Fanout = 7; REG Node = 'RegAndIntMode:inst\|IOCtrlReg\[3\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { RegAndIntMode:inst|IOCtrlReg[3] RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { RegAndIntMode:inst|IOCtrlReg[3] RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "IOW destination 4.500 ns + Shortest register " "Info: + Shortest clock path from clock IOW to destination register is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns IOW 1 CLK Pin_40 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_40; Fanout = 21; CLK Node = 'IOW'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { IOW } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 224 -96 72 240 "IOW" "" } { 216 72 106 232 "IOW" "" } { 256 688 776 272 "IOW" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.500 ns RegAndIntMode:inst\|IOCtrlReg\[3\] 2 REG LC77 7 " "Info: 2: + IC(1.000 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC77; Fanout = 7; REG Node = 'RegAndIntMode:inst\|IOCtrlReg\[3\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 77.78 % " "Info: Total cell delay = 3.500 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 22.22 % " "Info: Total interconnect delay = 1.000 ns ( 22.22 % )" {  } {  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "IOW source 4.500 ns - Longest register " "Info: - Longest clock path from clock IOW to source register is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns IOW 1 CLK Pin_40 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_40; Fanout = 21; CLK Node = 'IOW'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { IOW } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 224 -96 72 240 "IOW" "" } { 216 72 106 232 "IOW" "" } { 256 688 776 272 "IOW" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.500 ns RegAndIntMode:inst\|IOCtrlReg\[3\] 2 REG LC77 7 " "Info: 2: + IC(1.000 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC77; Fanout = 7; REG Node = 'RegAndIntMode:inst\|IOCtrlReg\[3\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 77.78 % " "Info: Total cell delay = 3.500 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 22.22 % " "Info: Total interconnect delay = 1.000 ns ( 22.22 % )" {  } {  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } }  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.000 ns + " "Info: + Micro setup delay of destination is 3.000 ns" {  } { { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } }  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { RegAndIntMode:inst|IOCtrlReg[3] RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register StartAdMode:inst4\|qn\[0\] register StartAdMode:inst4\|qn\[3\] 76.92 MHz 13.0 ns Internal " "Info: Clock Clk has Internal fmax of 76.92 MHz between source register StartAdMode:inst4\|qn\[0\] and destination register StartAdMode:inst4\|qn\[3\] (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns StartAdMode:inst4\|qn\[0\] 1 REG LC39 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC39; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[0\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { StartAdMode:inst4|qn[0] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 5.000 ns StartAdMode:inst4\|lpm_add_sub:i_rtl_1\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~8 2 COMB LC82 3 " "Info: 2: + IC(1.000 ns) + CELL(4.000 ns) = 5.000 ns; Loc. = LC82; Fanout = 3; COMB Node = 'StartAdMode:inst4\|lpm_add_sub:i_rtl_1\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~8'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "5.000 ns" { StartAdMode:inst4|qn[0] StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~8 } "NODE_NAME" } } } { "d:/program files/quartus4.0/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 9.000 ns StartAdMode:inst4\|qn\[3\] 3 REG LC114 29 " "Info: 3: + IC(1.000 ns) + CELL(3.000 ns) = 9.000 ns; Loc. = LC114; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[3\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~8 StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" {  } {  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "9.000 ns" { StartAdMode:inst4|qn[0] StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~8 StartAdMode:inst4|qn[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock Clk to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk 1 CLK Pin_87 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = Pin_87; Fanout = 19; CLK Node = 'Clk'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 168 1080 1248 184 "Clk" "" } { 232 1280 1320 248 "Clk" "" } { 160 1280 1320 176 "Clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns StartAdMode:inst4\|qn\[3\] 2 REG LC114 29 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC114; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[3\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.000 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 1.500 ns - Longest register " "Info: - Longest clock path from clock Clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk 1 CLK Pin_87 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = Pin_87; Fanout = 19; CLK Node = 'Clk'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 168 1080 1248 184 "Clk" "" } { 232 1280 1320 248 "Clk" "" } { 160 1280 1320 176 "Clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns StartAdMode:inst4\|qn\[0\] 2 REG LC39 29 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC39; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[0\]'" {  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.000 ns" { Clk StartAdMode:inst4|qn[0] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[0] } "NODE_NAME" } } }  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.000 ns + " "Info: + Micro setup delay of destination is 3.000 ns" {  } { { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } }  } 0}  } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "9.000 ns" { StartAdMode:inst4|qn[0] StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~8 StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[0] } "NODE_NAME" } } }  } 0}