pc104_cpld.csf.qmsg

是关于对数据采集卡的基于PC104总线的读写程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 11 14:08:03 2006 " "Info: Processing started: Thu May 11 14:08:03 2006" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Pc104_Cpld -c Pc104_Cpld " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Pc104_Cpld -c Pc104_Cpld" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Pc104_Cpld.bdf 1 1 " "Info: Found 1 design units and 1 entities in source file Pc104_Cpld.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Pc104_Cpld " "Info: Found entity 1: Pc104_Cpld" {  } { { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "Pc104_Cpld" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AddressDecoder.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file AddressDecoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AddressDecoder-AddressDecoder_architecture " "Info: Found design unit 1: AddressDecoder-AddressDecoder_architecture" {  } { { "E:/Pc104_Cpld/AddressDecoder.vhd" "AddressDecoder-AddressDecoder_architecture" "" { Text "E:/Pc104_Cpld/AddressDecoder.vhd" 35 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 AddressDecoder " "Info: Found entity 1: AddressDecoder" {  } { { "E:/Pc104_Cpld/AddressDecoder.vhd" "AddressDecoder" "" { Text "E:/Pc104_Cpld/AddressDecoder.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RegAndIntMode.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file RegAndIntMode.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RegAndIntMode-RegAndIntMode_architecture " "Info: Found design unit 1: RegAndIntMode-RegAndIntMode_architecture" {  } { { "E:/Pc104_Cpld/RegAndIntMode.vhd" "RegAndIntMode-RegAndIntMode_architecture" "" { Text "E:/Pc104_Cpld/RegAndIntMode.vhd" 33 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 RegAndIntMode " "Info: Found entity 1: RegAndIntMode" {  } { { "E:/Pc104_Cpld/RegAndIntMode.vhd" "RegAndIntMode" "" { Text "E:/Pc104_Cpld/RegAndIntMode.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "StartAdMode.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file StartAdMode.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 StartAdMode-StartAdMode_architecture " "Info: Found design unit 1: StartAdMode-StartAdMode_architecture" {  } { { "E:/Pc104_Cpld/StartAdMode.vhd" "StartAdMode-StartAdMode_architecture" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 26 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 StartAdMode " "Info: Found entity 1: StartAdMode" {  } { { "E:/Pc104_Cpld/StartAdMode.vhd" "StartAdMode" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "AdToFifo.vhd 2 1 " "Info: Found 2 design units and 1 entities in source file AdToFifo.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AdToFifo-AdToFifo_architecture " "Info: Found design unit 1: AdToFifo-AdToFifo_architecture" {  } { { "E:/Pc104_Cpld/AdToFifo.vhd" "AdToFifo-AdToFifo_architecture" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 22 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 AdToFifo " "Info: Found entity 1: AdToFifo" {  } { { "E:/Pc104_Cpld/AdToFifo.vhd" "AdToFifo" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "qn AdToFifo.vhd(71) " "Warning: VHDL Process Statement warning at AdToFifo.vhd(71): signal qn is in statement, but is not in sensitivity list" {  } { { "E:/Pc104_Cpld/AdToFifo.vhd" "" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 71 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "AdToFifo.vhd(80) " "Info: VHDL Case Statement information at AdToFifo.vhd(80): OTHERS choice is never selected" {  } { { "E:/Pc104_Cpld/AdToFifo.vhd" "" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 80 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "fifointflag RegAndIntMode.vhd(39) " "Warning: VHDL Signal Declaration warning at RegAndIntMode.vhd(39): used implicit default value for signal fifointflag because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 39 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "AdToFifo:inst6\|qn\[0\]~0 8 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: AdToFifo:inst6\|qn\[0\]~0" {  } { { "E:/Pc104_Cpld/AdToFifo.vhd" "" "qn\[0\]~0" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 30 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } }  } 0}  } {  } 0}