pc104_cpld.map.rpt

是关于对数据采集卡的基于PC104总线的读写程序

           |-- altshift:oflow_ext_latency_ffs
           |-- altshift:result_ext_latency_ffs
 |-- AdToFifo:inst6
      |-- lpm_counter:qn_rtl_0


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node            ; Macrocells ; Pins ; Full Hierarchy Name                                                                        ;
+---------------------------------------+------------+------+--------------------------------------------------------------------------------------------+
; |Pc104_Cpld                           ; 69         ; 51   ; |Pc104_Cpld                                                                                ;
;    |AdToFifo:inst6|                   ; 18         ; 0    ; |Pc104_Cpld|AdToFifo:inst6                                                                 ;
;       |lpm_counter:qn_rtl_0|          ; 8          ; 0    ; |Pc104_Cpld|AdToFifo:inst6|lpm_counter:qn_rtl_0                                            ;
;    |AddressDecoder:inst3|             ; 9          ; 0    ; |Pc104_Cpld|AddressDecoder:inst3                                                           ;
;    |RegAndIntMode:inst|               ; 27         ; 0    ; |Pc104_Cpld|RegAndIntMode:inst                                                             ;
;    |StartAdMode:inst4|                ; 14         ; 0    ; |Pc104_Cpld|StartAdMode:inst4                                                              ;
;       |lpm_add_sub:i_rtl_1|           ; 1          ; 0    ; |Pc104_Cpld|StartAdMode:inst4|lpm_add_sub:i_rtl_1                                          ;
;          |addcore:adder[0]|           ; 1          ; 0    ; |Pc104_Cpld|StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]                         ;
;             |a_csnbuffer:result_node| ; 1          ; 0    ; |Pc104_Cpld|StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]|a_csnbuffer:result_node ;
+---------------------------------------+------------+------+--------------------------------------------------------------------------------------------+


+---------------------------------+
; Analysis & Synthesis Equations  ;
+---------------------------------+
The equations can be found in E:/Pc104_Cpld/Pc104_Cpld.map.eqn.


+----------------------------------------------------------------------------+
; Analysis & Synthesis Files Read                                            ;
+-----------------------------------------------------------------------------
; File Name                                                           ; Read ;
+---------------------------------------------------------------------+------+
; Pc104_Cpld.bdf                                                      ; Read ;
; AddressDecoder.vhd                                                  ; Read ;
; RegAndIntMode.vhd                                                   ; Read ;
; StartAdMode.vhd                                                     ; Read ;
; AdToFifo.vhd                                                        ; Read ;
; d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf ; Read ;
; d:/program files/quartus4.0/libraries/megafunctions/lpm_add_sub.tdf ; Read ;
; d:/program files/quartus4.0/libraries/megafunctions/addcore.tdf     ; Read ;
; d:/program files/quartus4.0/libraries/megafunctions/a_csnbuffer.tdf ; Read ;
; d:/program files/quartus4.0/libraries/megafunctions/look_add.tdf    ; Read ;
; d:/program files/quartus4.0/libraries/megafunctions/altshift.tdf    ; Read ;
+---------------------------------------------------------------------+------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 69                   ;
; Total registers      ; 35                   ;
; I/O pins             ; 51                   ;
; Shareable expanders  ; 2                    ;
; Parallel expanders   ; 5                    ;
; Maximum fan-out node ; SA[9]                ;
; Maximum fan-out      ; 40                   ;
; Total fan-out        ; 834                  ;
; Average fan-out      ; 6.84                 ;
+----------------------+----------------------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Thu May 11 14:08:03 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Pc104_Cpld -c Pc104_Cpld
Info: Found 1 design units and 1 entities in source file Pc104_Cpld.bdf
    Info: Found entity 1: Pc104_Cpld
Info: Found 2 design units and 1 entities in source file AddressDecoder.vhd
    Info: Found design unit 1: AddressDecoder-AddressDecoder_architecture
    Info: Found entity 1: AddressDecoder
Info: Found 2 design units and 1 entities in source file RegAndIntMode.vhd
    Info: Found design unit 1: RegAndIntMode-RegAndIntMode_architecture
    Info: Found entity 1: RegAndIntMode
Info: Found 2 design units and 1 entities in source file StartAdMode.vhd
    Info: Found design unit 1: StartAdMode-StartAdMode_architecture
    Info: Found entity 1: StartAdMode
Info: Found 2 design units and 1 entities in source file AdToFifo.vhd
    Info: Found design unit 1: AdToFifo-AdToFifo_architecture
    Info: Found entity 1: AdToFifo
Warning: VHDL Process Statement warning at AdToFifo.vhd(71): signal qn is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at AdToFifo.vhd(80): OTHERS choice is never selected
Warning: VHDL Signal Declaration warning at RegAndIntMode.vhd(39): used implicit default value for signal fifointflag because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=8) from the following logic: AdToFifo:inst6|qn[0]~0
Info: Found 1 design units and 1 entities in source file d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file d:/program files/quartus4.0/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file d:/program files/quartus4.0/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file d:/program files/quartus4.0/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file d:/program files/quartus4.0/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units and 1 entities in source file d:/program files/quartus4.0/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 10 buffer(s)
    Info: Ignored 10 SOFT buffer(s)
Info: Registers with preset signals will power-up high
Warning: Output pins are stuck at VCC or GND
    Warning: Pin CpldState stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin Clk to global clock signal
Info: Implemented 122 device resources after synthesis - the final resource count might be different
    Info: Implemented 24 input pins
    Info: Implemented 19 output pins
    Info: Implemented 8 bidirectional pins
    Info: Implemented 69 macrocells
    Info: Implemented 2 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Thu May 11 14:08:17 2006
    Info: Elapsed time: 00:00:14