pc104_cpld.map.eqn

是关于对数据采集卡的基于PC104总线的读写程序

--B1L6 is RegAndIntMode:inst|i67~240
B1L6_p0_out = !IOR & !AEN & !SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[2];
B1L6_p2_out = B1_IntEnReg[2] & !IOR & !AEN & SA[0] & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[2];
B1L6_p3_out = !IOR & !AEN & !SA[0] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[2] & !FF;
B1L6_p4_out = !B1_IntEnReg[2] & !IOR & !AEN & SA[0] & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[2];
B1L6_or_out = B1L7 # B1L6_p0_out # B1L6_p2_out # B1L6_p3_out # B1L6_p4_out;
B1L6 = B1_IOCtrlReg[2] $ B1L6_or_out;


--B1L21 is RegAndIntMode:inst|i72~18
B1L21_p1_out = !AEN & !IOR & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8];
B1L21_p2_out = !IOR & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & SA[0] & SA[1];
B1L21_or_out = B1L21_p1_out # B1L21_p2_out;
B1L21 = B1L21_or_out;


--B1L8 is RegAndIntMode:inst|i69~238
B1L8 = EXP(!IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8]);


--B1L9 is RegAndIntMode:inst|i69~243
B1L9_p1_out = HF & !IOR & !AEN & !SA[0] & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8];
B1L9_p2_out = !IOR & !AEN & SA[0] & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IntEnReg[1];
B1L9_p3_out = SA[0] & SA[1] & B1_IOCtrlReg[1];
B1L9_p4_out = B1_IOCtrlReg[1] & B1L8;
B1L9_or_out = B1L9_p1_out # B1L9_p2_out # B1L9_p3_out # B1L9_p4_out;
B1L9 = B1L9_or_out;


--B1L01 is RegAndIntMode:inst|i71~238
B1L01_p0_out = !IOR & !AEN & !SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[0];
B1L01_p2_out = B1_IntEnReg[0] & !IOR & !AEN & SA[0] & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[0];
B1L01_p3_out = !IOR & !AEN & !SA[0] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[0] & !EF;
B1L01_p4_out = !B1_IntEnReg[0] & !IOR & !AEN & SA[0] & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[0];
B1L01_or_out = B1L11 # B1L01_p0_out # B1L01_p2_out # B1L01_p3_out # B1L01_p4_out;
B1L01 = B1_IOCtrlReg[0] $ B1L01_or_out;


--C1L1 is AddressDecoder:inst3|i15~13
C1L1_p1_out = !AEN & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8];
C1L1_or_out = C1L1_p1_out;
C1L1 = !(C1L1_or_out);


--C1L2 is AddressDecoder:inst3|i34~14
C1L2_p1_out = !SA[3] & !SA[2] & !AEN & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8];
C1L2_or_out = C1L2_p1_out;
C1L2 = !(C1L2_or_out);


--C1L3 is AddressDecoder:inst3|i140~16
C1L3_p1_out = SA[3] & !SA[2] & !AEN & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !SA[0] & !SA[1] & !IOR;
C1L3_or_out = C1L3_p1_out;
C1L3 = !(C1L3_or_out);


--C1L4 is AddressDecoder:inst3|i164~16
C1L4_p1_out = !SBHE & SA[3] & !SA[2] & !AEN & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !SA[0] & !SA[1];
C1L4_or_out = C1L4_p1_out;
C1L4 = !(C1L4_or_out);


--C1L9 is AddressDecoder:inst3|i192~72
C1L9_p1_out = !IOW & !SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8];
C1L9_or_out = C1L9_p1_out # RESET;
C1L9 = !(C1L9_or_out);


--C1L5 is AddressDecoder:inst3|i164~19
C1L5_p1_out = !SBHE & SA[3] & !SA[2] & !AEN & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !SA[0] & !SA[1];
C1L5_or_out = C1L5_p1_out;
C1L5 = !(C1L5_or_out);


--C1L6 is AddressDecoder:inst3|i164~22
C1L6_p1_out = !SBHE & SA[3] & !SA[2] & !AEN & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !SA[0] & !SA[1];
C1L6_or_out = C1L6_p1_out;
C1L6 = !(C1L6_or_out);


--C1L7 is AddressDecoder:inst3|i164~25
C1L7_p1_out = !SBHE & SA[3] & !SA[2] & !AEN & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !SA[0] & !SA[1];
C1L7_or_out = C1L7_p1_out;
C1L7 = !(C1L7_or_out);


--B1_IntEnReg[7] is RegAndIntMode:inst|IntEnReg[7]
B1_IntEnReg[7]_p1_out = A1L12 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IntEnReg[7];
B1_IntEnReg[7]_p4_out = !A1L12 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IntEnReg[7];
B1_IntEnReg[7]_or_out = B1_IntEnReg[7]_p1_out # B1_IntEnReg[7]_p4_out;
B1_IntEnReg[7]_reg_input = B1_IntEnReg[7]_or_out;
B1_IntEnReg[7] = TFFE(B1_IntEnReg[7]_reg_input, IOW, !C1L01, , );


--C1L01 is AddressDecoder:inst3|i192~75
C1L01 = EXP(!RESET & C1L8);


--B1_IntEnReg[6] is RegAndIntMode:inst|IntEnReg[6]
B1_IntEnReg[6]_p1_out = A1L22 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IntEnReg[6];
B1_IntEnReg[6]_p4_out = !A1L22 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IntEnReg[6];
B1_IntEnReg[6]_or_out = B1_IntEnReg[6]_p1_out # B1_IntEnReg[6]_p4_out;
B1_IntEnReg[6]_reg_input = B1_IntEnReg[6]_or_out;
B1_IntEnReg[6] = TFFE(B1_IntEnReg[6]_reg_input, IOW, !C1L01, , );


--B1_IntEnReg[5] is RegAndIntMode:inst|IntEnReg[5]
B1_IntEnReg[5]_p1_out = A1L32 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IntEnReg[5];
B1_IntEnReg[5]_p4_out = !A1L32 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IntEnReg[5];
B1_IntEnReg[5]_or_out = B1_IntEnReg[5]_p1_out # B1_IntEnReg[5]_p4_out;
B1_IntEnReg[5]_reg_input = B1_IntEnReg[5]_or_out;
B1_IntEnReg[5] = TFFE(B1_IntEnReg[5]_reg_input, IOW, !C1L01, , );


--B1_IntEnReg[4] is RegAndIntMode:inst|IntEnReg[4]
B1_IntEnReg[4]_p1_out = A1L42 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IntEnReg[4];
B1_IntEnReg[4]_p4_out = !A1L42 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IntEnReg[4];
B1_IntEnReg[4]_or_out = B1_IntEnReg[4]_p1_out # B1_IntEnReg[4]_p4_out;
B1_IntEnReg[4]_reg_input = B1_IntEnReg[4]_or_out;
B1_IntEnReg[4] = TFFE(B1_IntEnReg[4]_reg_input, IOW, !C1L01, , );


--B1_IntEnReg[3] is RegAndIntMode:inst|IntEnReg[3]
B1_IntEnReg[3]_p1_out = A1L52 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IntEnReg[3];
B1_IntEnReg[3]_p4_out = !A1L52 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IntEnReg[3];
B1_IntEnReg[3]_or_out = B1_IntEnReg[3]_p1_out # B1_IntEnReg[3]_p4_out;
B1_IntEnReg[3]_reg_input = B1_IntEnReg[3]_or_out;
B1_IntEnReg[3] = TFFE(B1_IntEnReg[3]_reg_input, IOW, !C1L01, , );


--B1_IntEnReg[2] is RegAndIntMode:inst|IntEnReg[2]
B1_IntEnReg[2]_p1_out = A1L62 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IntEnReg[2];
B1_IntEnReg[2]_p4_out = !A1L62 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IntEnReg[2];
B1_IntEnReg[2]_or_out = B1_IntEnReg[2]_p1_out # B1_IntEnReg[2]_p4_out;
B1_IntEnReg[2]_reg_input = B1_IntEnReg[2]_or_out;
B1_IntEnReg[2] = TFFE(B1_IntEnReg[2]_reg_input, IOW, !C1L01, , );


--B1_IntEnReg[1] is RegAndIntMode:inst|IntEnReg[1]
B1_IntEnReg[1]_p1_out = A1L72 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IntEnReg[1];
B1_IntEnReg[1]_p4_out = !A1L72 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IntEnReg[1];
B1_IntEnReg[1]_or_out = B1_IntEnReg[1]_p1_out # B1_IntEnReg[1]_p4_out;
B1_IntEnReg[1]_reg_input = B1_IntEnReg[1]_or_out;
B1_IntEnReg[1] = TFFE(B1_IntEnReg[1]_reg_input, IOW, !C1L01, , );


--B1_IntEnReg[0] is RegAndIntMode:inst|IntEnReg[0]
B1_IntEnReg[0]_p1_out = A1L82 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IntEnReg[0];
B1_IntEnReg[0]_p4_out = !A1L82 & SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IntEnReg[0];
B1_IntEnReg[0]_or_out = B1_IntEnReg[0]_p1_out # B1_IntEnReg[0]_p4_out;
B1_IntEnReg[0]_reg_input = B1_IntEnReg[0]_or_out;
B1_IntEnReg[0] = TFFE(B1_IntEnReg[0]_reg_input, IOW, !C1L01, , );


--B1_IOCtrlReg[7] is RegAndIntMode:inst|IOCtrlReg[7]
B1_IOCtrlReg[7]_p1_out = A1L12 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[7];
B1_IOCtrlReg[7]_p4_out = !A1L12 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[7];
B1_IOCtrlReg[7]_or_out = B1_IOCtrlReg[7]_p1_out # B1_IOCtrlReg[7]_p4_out;
B1_IOCtrlReg[7]_reg_input = B1_IOCtrlReg[7]_or_out;
B1_IOCtrlReg[7] = TFFE(B1_IOCtrlReg[7]_reg_input, IOW, !C1L01, , );


--B1_IOCtrlReg[6] is RegAndIntMode:inst|IOCtrlReg[6]
B1_IOCtrlReg[6]_p1_out = A1L22 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[6];
B1_IOCtrlReg[6]_p4_out = !A1L22 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[6];
B1_IOCtrlReg[6]_or_out = B1_IOCtrlReg[6]_p1_out # B1_IOCtrlReg[6]_p4_out;
B1_IOCtrlReg[6]_reg_input = B1_IOCtrlReg[6]_or_out;
B1_IOCtrlReg[6] = TFFE(B1_IOCtrlReg[6]_reg_input, IOW, !C1L01, , );


--B1_IOCtrlReg[5] is RegAndIntMode:inst|IOCtrlReg[5]
B1_IOCtrlReg[5]_p1_out = A1L32 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[5];
B1_IOCtrlReg[5]_p4_out = !A1L32 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[5];
B1_IOCtrlReg[5]_or_out = B1_IOCtrlReg[5]_p1_out # B1_IOCtrlReg[5]_p4_out;
B1_IOCtrlReg[5]_reg_input = B1_IOCtrlReg[5]_or_out;
B1_IOCtrlReg[5] = TFFE(B1_IOCtrlReg[5]_reg_input, IOW, !C1L01, , );


--B1_IOCtrlReg[4] is RegAndIntMode:inst|IOCtrlReg[4]
B1_IOCtrlReg[4]_p1_out = A1L42 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[4];
B1_IOCtrlReg[4]_p4_out = !A1L42 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[4];
B1_IOCtrlReg[4]_or_out = B1_IOCtrlReg[4]_p1_out # B1_IOCtrlReg[4]_p4_out;
B1_IOCtrlReg[4]_reg_input = B1_IOCtrlReg[4]_or_out;
B1_IOCtrlReg[4] = TFFE(B1_IOCtrlReg[4]_reg_input, IOW, !C1L01, , );


--B1_IOCtrlReg[3] is RegAndIntMode:inst|IOCtrlReg[3]
B1_IOCtrlReg[3]_p1_out = A1L52 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[3];
B1_IOCtrlReg[3]_p4_out = !A1L52 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[3];
B1_IOCtrlReg[3]_or_out = B1_IOCtrlReg[3]_p1_out # B1_IOCtrlReg[3]_p4_out;
B1_IOCtrlReg[3]_reg_input = B1_IOCtrlReg[3]_or_out;
B1_IOCtrlReg[3] = TFFE(B1_IOCtrlReg[3]_reg_input, IOW, !C1L01, , );


--L1_dffs[1] is AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[1]
L1_dffs[1]_or_out = L1_dffs[0];
L1_dffs[1]_reg_input = L1_dffs[1]_or_out;
L1_dffs[1] = TFFE(L1_dffs[1]_reg_input, GLOBAL(Clk), !C1L01, , E1_Flag);


--D1L1 is StartAdMode:inst4|i6~41
D1L1_p1_out = !IOW & !SA[0] & !AEN & !SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !OUT_ST;
D1L1_p2_out = !OUT_ST & RESET;
D1L1_p3_out = !OUT_ST & D1L1;
D1L1_or_out = D1L1_p1_out # D1L1_p2_out # D1L1_p3_out;
D1L1 = D1L1_or_out;


--B1L1 is RegAndIntMode:inst|i57~161
B1L1_p2_out = B1_IntEnReg[7] & !SA[1] & !IOR & SA[0] & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[7];
B1L1_p3_out = !B1_IntEnReg[7] & !SA[1] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[7];
B1L1_p4_out = !IOR & !SA[0] & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[7];
B1L1_or_out = B1L1_p2_out # B1L1_p3_out # B1L1_p4_out;
B1L1 = B1_IOCtrlReg[7] $ B1L1_or_out;


--B1L2 is RegAndIntMode:inst|i59~157
B1L2_p2_out = B1_IntEnReg[6] & !SA[1] & SA[0] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[6];
B1L2_p3_out = !B1_IntEnReg[6] & !SA[1] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[6];
B1L2_p4_out = !SA[0] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[6];
B1L2_or_out = B1L2_p2_out # B1L2_p3_out # B1L2_p4_out;
B1L2 = B1_IOCtrlReg[6] $ B1L2_or_out;


--B1L3 is RegAndIntMode:inst|i61~157
B1L3_p2_out = B1_IntEnReg[5] & !SA[1] & SA[0] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[5];
B1L3_p3_out = !B1_IntEnReg[5] & !SA[1] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[5];
B1L3_p4_out = !SA[0] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[5];
B1L3_or_out = B1L3_p2_out # B1L3_p3_out # B1L3_p4_out;
B1L3 = B1_IOCtrlReg[5] $ B1L3_or_out;


--B1L4 is RegAndIntMode:inst|i63~157
B1L4_p2_out = B1_IntEnReg[4] & !SA[1] & SA[0] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[4];
B1L4_p3_out = !B1_IntEnReg[4] & !SA[1] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[4];
B1L4_p4_out = !SA[0] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[4];
B1L4_or_out = B1L4_p2_out # B1L4_p3_out # B1L4_p4_out;
B1L4 = B1_IOCtrlReg[4] $ B1L4_or_out;


--B1L5 is RegAndIntMode:inst|i65~157
B1L5_p2_out = B1_IntEnReg[3] & !SA[1] & SA[0] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[3];
B1L5_p3_out = !B1_IntEnReg[3] & !SA[1] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[3];
B1L5_p4_out = !SA[0] & !IOR & !AEN & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[3];
B1L5_or_out = B1L5_p2_out # B1L5_p3_out # B1L5_p4_out;
B1L5 = B1_IOCtrlReg[3] $ B1L5_or_out;


--L1_dffs[2] is AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[2]
L1_dffs[2]_p1_out = L1_dffs[0] & L1_dffs[1];
L1_dffs[2]_or_out = L1_dffs[2]_p1_out;
L1_dffs[2]_reg_input = L1_dffs[2]_or_out;
L1_dffs[2] = TFFE(L1_dffs[2]_reg_input, GLOBAL(Clk), !C1L01, , E1_Flag);


--L1_dffs[3] is AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[3]
L1_dffs[3]_p1_out = L1_dffs[2] & L1_dffs[0] & L1_dffs[1];
L1_dffs[3]_or_out = L1_dffs[3]_p1_out;
L1_dffs[3]_reg_input = L1_dffs[3]_or_out;
L1_dffs[3] = TFFE(L1_dffs[3]_reg_input, GLOBAL(Clk), !C1L01, , E1_Flag);


--B1_IOCtrlReg[2] is RegAndIntMode:inst|IOCtrlReg[2]
B1_IOCtrlReg[2]_p1_out = A1L62 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[2];
B1_IOCtrlReg[2]_p4_out = !A1L62 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[2];
B1_IOCtrlReg[2]_or_out = B1_IOCtrlReg[2]_p1_out # B1_IOCtrlReg[2]_p4_out;
B1_IOCtrlReg[2]_reg_input = B1_IOCtrlReg[2]_or_out;
B1_IOCtrlReg[2] = TFFE(B1_IOCtrlReg[2]_reg_input, IOW, !C1L01, , );


--B1_IOCtrlReg[1] is RegAndIntMode:inst|IOCtrlReg[1]
B1_IOCtrlReg[1]_p1_out = A1L72 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[1];
B1_IOCtrlReg[1]_p4_out = !A1L72 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[1];
B1_IOCtrlReg[1]_or_out = B1_IOCtrlReg[1]_p1_out # B1_IOCtrlReg[1]_p4_out;
B1_IOCtrlReg[1]_reg_input = B1_IOCtrlReg[1]_or_out;
B1_IOCtrlReg[1] = TFFE(B1_IOCtrlReg[1]_reg_input, IOW, !C1L01, , );


--B1_IOCtrlReg[0] is RegAndIntMode:inst|IOCtrlReg[0]
B1_IOCtrlReg[0]_p1_out = A1L82 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & !B1_IOCtrlReg[0];
B1_IOCtrlReg[0]_p4_out = !A1L82 & SA[0] & SA[1] & !SA[3] & SA[2] & !SA[4] & !SA[5] & !SA[6] & !SA[7] & SA[9] & SA[8] & B1_IOCtrlReg[0];
B1_IOCtrlReg[0]_or_out = B1_IOCtrlReg[0]_p1_out # B1_IOCtrlReg[0]_p4_out;
B1_IOCtrlReg[0]_reg_input = B1_IOCtrlReg[0]_or_out;
B1_IOCtrlReg[0] = TFFE(B1_IOCtrlReg[0]_reg_input, IOW, !C1L01, , );


--L1_dffs[4] is AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4]
L1_dffs[4]_p1_out = L1_dffs[3] & L1_dffs[2] & L1_dffs[0] & L1_dffs[1];
L1_dffs[4]_or_out = L1_dffs[4]_p1_out;
L1_dffs[4]_reg_input = L1_dffs[4]_or_out;
L1_dffs[4] = TFFE(L1_dffs[4]_reg_input, GLOBAL(Clk), !C1L01, , E1_Flag);