lcdmddr.tan.rpt
来自「128×64单色点阵LCD的quartus工程文件」· RPT 代码 · 共 227 行 · 第 1/5 页
RPT
227 行
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg4 ; lcdmpddr:inst|db[4] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg5 ; lcdmpddr:inst|db[4] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg6 ; lcdmpddr:inst|db[4] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg7 ; lcdmpddr:inst|db[4] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|db[6] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|stks[3] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|cntp[1] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|cntp[0] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[5] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[6] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[4] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[3] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[0] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[21] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[1] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[8] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[1] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[7] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[1] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[6] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[1] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[5] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|stks[0] ; lcdmpddr:inst|stks[3] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|cntp[0] ; lcdmpddr:inst|db[4] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[3] ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[21] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[16] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[17] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[19] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[18] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[20] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[1] ; lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[21] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[0] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[8] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[0] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[7] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[0] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[6] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[0] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[5] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[8] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[7] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[6] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[2] ; lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[5] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg0 ; lcdmpddr:inst|db[0] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg1 ; lcdmpddr:inst|db[0] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg2 ; lcdmpddr:inst|db[0] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg3 ; lcdmpddr:inst|db[0] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg4 ; lcdmpddr:inst|db[0] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg5 ; lcdmpddr:inst|db[0] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_address_reg6 ; lcdmpddr:inst|db[0] ; sclk ; sclk ; None ; None ; None ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ram_block1a8~porta_addre⌨️ 快捷键说明
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