lcdmddr.map.eqn

128×64单色点阵LCD的quartus工程文件

--operation mode is normal

B1L33 = B1_cntp[0] & B1_cntp[2] & !B1_cntp[1];


--H1_q_a[6] is pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 9
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[6]_PORT_A_address = BUS(B1L14, B1L24, B1L34, B1L44, B1L54, B1L64, B1L74, B1L84);
H1_q_a[6]_PORT_A_address_reg = DFFE(H1_q_a[6]_PORT_A_address, H1_q_a[6]_clock_0, , , );
H1_q_a[6]_clock_0 = sclk;
H1_q_a[6]_PORT_A_data_out = MEMORY(, , H1_q_a[6]_PORT_A_address_reg, , , , , , H1_q_a[6]_clock_0, , , , , );
H1_q_a[6] = H1_q_a[6]_PORT_A_data_out[0];


--B1L43 is lcdmpddr:inst|Mux~262
--operation mode is normal

B1L43 = B1_cntp[2] & B1_cntp[1];


--H1_q_a[5] is pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 9
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[5]_PORT_A_address = BUS(B1L14, B1L24, B1L34, B1L44, B1L54, B1L64, B1L74, B1L84);
H1_q_a[5]_PORT_A_address_reg = DFFE(H1_q_a[5]_PORT_A_address, H1_q_a[5]_clock_0, , , );
H1_q_a[5]_clock_0 = sclk;
H1_q_a[5]_PORT_A_data_out = MEMORY(, , H1_q_a[5]_PORT_A_address_reg, , , , , , H1_q_a[5]_clock_0, , , , , );
H1_q_a[5] = H1_q_a[5]_PORT_A_data_out[0];


--B1L62 is lcdmpddr:inst|Mux~114
--operation mode is normal

B1L62 = B1_cntp[0] & H1_q_a[5];


--B1L52 is lcdmpddr:inst|Mux~72
--operation mode is normal

B1L52 = !B1_cntp[0] & !B1_cntp[1];


--H1_q_a[4] is pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 9
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[4]_PORT_A_address = BUS(B1L14, B1L24, B1L34, B1L44, B1L54, B1L64, B1L74, B1L84);
H1_q_a[4]_PORT_A_address_reg = DFFE(H1_q_a[4]_PORT_A_address, H1_q_a[4]_clock_0, , , );
H1_q_a[4]_clock_0 = sclk;
H1_q_a[4]_PORT_A_data_out = MEMORY(, , H1_q_a[4]_PORT_A_address_reg, , , , , , H1_q_a[4]_clock_0, , , , , );
H1_q_a[4] = H1_q_a[4]_PORT_A_data_out[0];


--B1L72 is lcdmpddr:inst|Mux~115
--operation mode is normal

B1L72 = B1_cntp[0] & H1_q_a[4];


--H1_q_a[3] is pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 9
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[3]_PORT_A_address = BUS(B1L14, B1L24, B1L34, B1L44, B1L54, B1L64, B1L74, B1L84);
H1_q_a[3]_PORT_A_address_reg = DFFE(H1_q_a[3]_PORT_A_address, H1_q_a[3]_clock_0, , , );
H1_q_a[3]_clock_0 = sclk;
H1_q_a[3]_PORT_A_data_out = MEMORY(, , H1_q_a[3]_PORT_A_address_reg, , , , , , H1_q_a[3]_clock_0, , , , , );
H1_q_a[3] = H1_q_a[3]_PORT_A_data_out[0];


--B1L82 is lcdmpddr:inst|Mux~116
--operation mode is normal

B1L82 = B1_cntp[0] & H1_q_a[3];


--H1_q_a[2] is pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 9
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[2]_PORT_A_address = BUS(B1L14, B1L24, B1L34, B1L44, B1L54, B1L64, B1L74, B1L84);
H1_q_a[2]_PORT_A_address_reg = DFFE(H1_q_a[2]_PORT_A_address, H1_q_a[2]_clock_0, , , );
H1_q_a[2]_clock_0 = sclk;
H1_q_a[2]_PORT_A_data_out = MEMORY(, , H1_q_a[2]_PORT_A_address_reg, , , , , , H1_q_a[2]_clock_0, , , , , );
H1_q_a[2] = H1_q_a[2]_PORT_A_data_out[0];


--B1L92 is lcdmpddr:inst|Mux~117
--operation mode is normal

B1L92 = B1_cntp[0] & H1_q_a[2];


--B1L1 is lcdmpddr:inst|add~8
--operation mode is normal

B1L1 = B1_cntp[0] $ B1_cntp[1];


--H1_q_a[1] is pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 9
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[1]_PORT_A_address = BUS(B1L14, B1L24, B1L34, B1L44, B1L54, B1L64, B1L74, B1L84);
H1_q_a[1]_PORT_A_address_reg = DFFE(H1_q_a[1]_PORT_A_address, H1_q_a[1]_clock_0, , , );
H1_q_a[1]_clock_0 = sclk;
H1_q_a[1]_PORT_A_data_out = MEMORY(, , H1_q_a[1]_PORT_A_address_reg, , , , , , H1_q_a[1]_clock_0, , , , , );
H1_q_a[1] = H1_q_a[1]_PORT_A_data_out[0];


--B1L03 is lcdmpddr:inst|Mux~118
--operation mode is normal

B1L03 = B1_cntp[0] & H1_q_a[1];


--H1_q_a[0] is pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 9
--Port A Input: Registered, Port A Output: Un-registered
H1_q_a[0]_PORT_A_address = BUS(B1L14, B1L24, B1L34, B1L44, B1L54, B1L64, B1L74, B1L84);
H1_q_a[0]_PORT_A_address_reg = DFFE(H1_q_a[0]_PORT_A_address, H1_q_a[0]_clock_0, , , );
H1_q_a[0]_clock_0 = sclk;
H1_q_a[0]_PORT_A_data_out = MEMORY(, , H1_q_a[0]_PORT_A_address_reg, , , , , , H1_q_a[0]_clock_0, , , , , );
H1_q_a[0] = H1_q_a[0]_PORT_A_data_out[0];


--B1L13 is lcdmpddr:inst|Mux~119
--operation mode is normal

B1L13 = B1_cntp[0] & H1_q_a[0];


--B1L2 is lcdmpddr:inst|add~10
--operation mode is normal

B1L2 = B1_cntp[0] & B1_cntp[1];


--B1L95 is lcdmpddr:inst|stks~250
--operation mode is normal

B1L95 = !B1_stks[1] & !clear;


--B1_stks[3] is lcdmpddr:inst|stks[3]
--operation mode is normal

B1_stks[3]_lut_out = B1L16 & (B1_cntp[2] & !B1L33 # !B1_stks[3]);
B1_stks[3] = DFFEA(B1_stks[3]_lut_out, F1_safe_q[15], VCC, , , , );


--F1_safe_q[20] is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[20]
--operation mode is arithmetic

F1_safe_q[20]_carry_eqn = F1L04;
F1_safe_q[20]_lut_out = F1_safe_q[20] $ !F1_safe_q[20]_carry_eqn;
F1_safe_q[20]_reg_input = !clear & F1_safe_q[20]_lut_out;
F1_safe_q[20] = DFFEA(F1_safe_q[20]_reg_input, sclk, VCC, , , , );

--F1L24 is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|counter_cella20~COUT
--operation mode is arithmetic

F1L24 = CARRY(F1_safe_q[20] & !F1L04);


--F1_safe_q[19] is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[19]
--operation mode is arithmetic

F1_safe_q[19]_carry_eqn = F1L83;
F1_safe_q[19]_lut_out = F1_safe_q[19] $ F1_safe_q[19]_carry_eqn;
F1_safe_q[19]_reg_input = !clear & F1_safe_q[19]_lut_out;
F1_safe_q[19] = DFFEA(F1_safe_q[19]_reg_input, sclk, VCC, , , , );

--F1L04 is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|counter_cella19~COUT
--operation mode is arithmetic

F1L04 = CARRY(!F1L83 # !F1_safe_q[19]);


--F1_safe_q[18] is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[18]
--operation mode is arithmetic

F1_safe_q[18]_carry_eqn = F1L63;
F1_safe_q[18]_lut_out = F1_safe_q[18] $ !F1_safe_q[18]_carry_eqn;
F1_safe_q[18]_reg_input = !clear & F1_safe_q[18]_lut_out;
F1_safe_q[18] = DFFEA(F1_safe_q[18]_reg_input, sclk, VCC, , , , );

--F1L83 is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|counter_cella18~COUT
--operation mode is arithmetic

F1L83 = CARRY(F1_safe_q[18] & !F1L63);


--B1L3 is lcdmpddr:inst|clkm~0
--operation mode is normal

B1L3 = sel[0] & (sel[1] # F1_safe_q[19]) # !sel[0] & !sel[1] & F1_safe_q[18];


--F1_safe_q[21] is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[21]
--operation mode is normal

F1_safe_q[21]_carry_eqn = F1L24;
F1_safe_q[21]_lut_out = F1_safe_q[21] $ F1_safe_q[21]_carry_eqn;
F1_safe_q[21]_reg_input = !clear & F1_safe_q[21]_lut_out;
F1_safe_q[21] = DFFEA(F1_safe_q[21]_reg_input, sclk, VCC, , , , );


--B1L4 is lcdmpddr:inst|clkm~1
--operation mode is normal

B1L4 = B1L3 & (F1_safe_q[21] # !sel[1]) # !B1L3 & F1_safe_q[20] & sel[1];


--F1_safe_q[14] is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[14]
--operation mode is arithmetic

F1_safe_q[14]_carry_eqn = F1L82;
F1_safe_q[14]_lut_out = F1_safe_q[14] $ !F1_safe_q[14]_carry_eqn;
F1_safe_q[14]_reg_input = !clear & F1_safe_q[14]_lut_out;
F1_safe_q[14] = DFFEA(F1_safe_q[14]_reg_input, sclk, VCC, , , , );

--F1L03 is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|counter_cella14~COUT
--operation mode is arithmetic

F1L03 = CARRY(F1_safe_q[14] & !F1L82);


--B1L05 is lcdmpddr:inst|r_w~3
--operation mode is normal

B1L05 = !B1_stks[2] & !B1_stks[0];


--B1_ssk[0] is lcdmpddr:inst|ssk[0]
--operation mode is normal

B1_ssk[0]_lut_out = B1_dbnc & !clear & !B1_ssk[0] & !B1_ssk[1];
B1_ssk[0] = DFFEA(B1_ssk[0]_lut_out, F1_safe_q[15], VCC, , , , );


--B1L06 is lcdmpddr:inst|stks~251
--operation mode is normal

B1L06 = B1_ssk[0] & (!B1_cntp[2] # !B1_stks[3]) # !B1_ssk[0] & B1_stks[3] & !B1_cntp[2];


--B1L14 is lcdmpddr:inst|promadr[0]~24
--operation mode is normal

B1L14 = E1_safe_q[0] & (B1L42 # !B1L73 & !B1L93) # !E1_safe_q[0] & !B1L73 & !B1L93;


--B1L24 is lcdmpddr:inst|promadr[1]~413
--operation mode is normal

B1L24 = E1_safe_q[1] & B1L42 & (B1L73 # B1L93);


--B1L34 is lcdmpddr:inst|promadr[2]~26
--operation mode is normal

B1L34 = E1_safe_q[2] # !B1L73 & !B1L93 # !B1L42;


--B1L44 is lcdmpddr:inst|promadr[3]~414
--operation mode is normal

B1L44 = E1_safe_q[3] & (B1L73 # B1L93) # !E1_safe_q[3] & !B1L42 & (B1L73 # B1L93);


--B1L54 is lcdmpddr:inst|promadr[4]~415
--operation mode is normal

B1L54 = E1_safe_q[4] & B1L42 & (B1L73 # B1L93);


--B1L64 is lcdmpddr:inst|promadr[5]~416
--operation mode is normal

B1L64 = E1_safe_q[5] & B1L42 & (B1L73 # B1L93);


--B1L74 is lcdmpddr:inst|promadr[6]~417
--operation mode is normal

B1L74 = E1_safe_q[6] & (!E1_safe_q[8] # !E1_safe_q[7]) # !E1_safe_q[6] & (E1_safe_q[7] $ E1_safe_q[8]);


--B1L84 is lcdmpddr:inst|promadr[7]~418
--operation mode is normal

B1L84 = E1_safe_q[7] & E1_safe_q[8];


--B1L04 is lcdmpddr:inst|process3~0
--operation mode is normal

B1L04 = B1_stks[3] & (B1_cntp[1] # !B1_cntp[2] # !B1_cntp[0]);


--B1L01 is lcdmpddr:inst|cntp[2]~0
--operation mode is normal

B1L01 = B1_cntp[0] & B1_cntp[1] & B1_stks[3];


--B1L16 is lcdmpddr:inst|stks~253
--operation mode is normal

B1L16 = B1L95 & !B1_stks[0] & (B1_stks[2] $ B1_stks[3]);


--F1_safe_q[17] is lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[17]
--operation mode is arithmetic

F1_safe_q[17]_carry_eqn = F1L43;
F1_safe_q[17]_lut_out = F1_safe_q[17] $ F1_safe_q[17]_carry_eqn;
F1_safe_q[17]_reg_input = !clear & F1_safe_q[17]_lut_out;
F1_safe_q[17] = DFFEA(F1_safe_q[17]_reg_input, sclk, VCC, , , , );