lcdmddr.map.qmsg

128×64单色点阵LCD的quartus工程文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 13 14:21:21 2006 " "Info: Processing started: Thu Jul 13 14:21:21 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off lcdmddr -c lcdmddr " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off lcdmddr -c lcdmddr" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcdmpddr/lcdmpddr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lcdmpddr/lcdmpddr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lcdmpddr-lcdmpddr_arch " "Info: Found design unit 1: lcdmpddr-lcdmpddr_arch" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "lcdmpddr-lcdmpddr_arch" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lcdmpddr " "Info: Found entity 1: lcdmpddr" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "lcdmpddr" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pprom6x8/pprom6x8.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pprom6x8/pprom6x8.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pprom6x8-SYN " "Info: Found design unit 1: pprom6x8-SYN" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/pprom6x8/pprom6x8.vhd" "pprom6x8-SYN" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/pprom6x8/pprom6x8.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 pprom6x8 " "Info: Found entity 1: pprom6x8" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/pprom6x8/pprom6x8.vhd" "pprom6x8" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/pprom6x8/pprom6x8.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lcdmddr.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file lcdmddr.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 lcdmddr " "Info: Found entity 1: lcdmddr" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/lcdmddr.bdf" "lcdmddr" "" { Schematic "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/lcdmddr.bdf" { } } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "scount lcdmpddr.vhd(41) " "Warning: VHDL Process Statement warning at lcdmpddr.vhd(41): signal scount is in statement, but is not in sensitivity list" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 41 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "scount lcdmpddr.vhd(42) " "Warning: VHDL Process Statement warning at lcdmpddr.vhd(42): signal scount is in statement, but is not in sensitivity list" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 42 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "scount lcdmpddr.vhd(43) " "Warning: VHDL Process Statement warning at lcdmpddr.vhd(43): signal scount is in statement, but is not in sensitivity list" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 43 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "scount lcdmpddr.vhd(44) " "Warning: VHDL Process Statement warning at lcdmpddr.vhd(44): signal scount is in statement, but is not in sensitivity list" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 44 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "lcdmpddr.vhd(95) " "Info: VHDL Case Statement information at lcdmpddr.vhd(95): OTHERS choice is never selected" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 95 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "g:/quartus41/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file g:/quartus41/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "g:/quartus41/libraries/megafunctions/altsyncram.tdf" "altsyncram" "" { Text "g:/quartus41/libraries/megafunctions/altsyncram.tdf" 431 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_gkq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gkq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_gkq " "Info: Found entity 1: altsyncram_gkq" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/altsyncram_gkq.tdf" "altsyncram_gkq" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/altsyncram_gkq.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "lcdmpddr:inst\|cntm\[0\]~63 9 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: lcdmpddr:inst\|cntm\[0\]~63" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "cntm\[0\]~63" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 63 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "lcdmpddr:inst\|scount\[0\]~27 27 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=27) from the following logic: lcdmpddr:inst\|scount\[0\]~27" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" "" "scount\[0\]~27" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmpddr/lcdmpddr.vhd" 29 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "g:/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file g:/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "g:/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "g:/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_sv7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_sv7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_sv7 " "Info: Found entity 1: cntr_sv7" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/cntr_sv7.tdf" "cntr_sv7" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/cntr_sv7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_lc7.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_lc7.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_lc7 " "Info: Found entity 1: cntr_lc7" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/cntr_lc7.tdf" "cntr_lc7" "" { Text "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/cntr_lc7.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "113 " "Info: Implemented 113 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "88 " "Info: Implemented 88 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "9 " "Info: Implemented 9 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 14:21:29 2006 " "Info: Processing ended: Thu Jul 13 14:21:29 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0}  } {  } 0}