lcdmddr.hier_info

128×64单色点阵LCD的quartus工程文件

|lcdmddr
lcden <= lcdmpddr:inst.en
sclk => lcdmpddr:inst.sclk
sclk => pprom6x8:inst2.clock
start => lcdmpddr:inst.start
clear => lcdmpddr:inst.clear
sel[0] => lcdmpddr:inst.sel[0]
sel[1] => lcdmpddr:inst.sel[1]
lcdr/w <= lcdmpddr:inst.r_w
lcdd/i <= lcdmpddr:inst.d_i
lcdd[0] <= lcdmpddr:inst.db[0]
lcdd[1] <= lcdmpddr:inst.db[1]
lcdd[2] <= lcdmpddr:inst.db[2]
lcdd[3] <= lcdmpddr:inst.db[3]
lcdd[4] <= lcdmpddr:inst.db[4]
lcdd[5] <= lcdmpddr:inst.db[5]
lcdd[6] <= lcdmpddr:inst.db[6]
lcdd[7] <= lcdmpddr:inst.db[7]


|lcdmddr|lcdmpddr:inst
sclk => scount[25].CLK
sclk => scount[24].CLK
sclk => scount[23].CLK
sclk => scount[22].CLK
sclk => scount[21].CLK
sclk => scount[20].CLK
sclk => scount[19].CLK
sclk => scount[18].CLK
sclk => scount[17].CLK
sclk => scount[16].CLK
sclk => scount[15].CLK
sclk => scount[14].CLK
sclk => scount[13].CLK
sclk => scount[12].CLK
sclk => scount[11].CLK
sclk => scount[10].CLK
sclk => scount[9].CLK
sclk => scount[8].CLK
sclk => scount[7].CLK
sclk => scount[6].CLK
sclk => scount[5].CLK
sclk => scount[4].CLK
sclk => scount[3].CLK
sclk => scount[2].CLK
sclk => scount[1].CLK
sclk => scount[0].CLK
sclk => scount[26].CLK
start => dbnc~0.IN1
clear => scount~0.OUTPUTSELECT
clear => scount~1.OUTPUTSELECT
clear => scount~2.OUTPUTSELECT
clear => scount~3.OUTPUTSELECT
clear => scount~4.OUTPUTSELECT
clear => scount~5.OUTPUTSELECT
clear => scount~6.OUTPUTSELECT
clear => scount~7.OUTPUTSELECT
clear => scount~8.OUTPUTSELECT
clear => scount~9.OUTPUTSELECT
clear => scount~10.OUTPUTSELECT
clear => scount~11.OUTPUTSELECT
clear => scount~12.OUTPUTSELECT
clear => scount~13.OUTPUTSELECT
clear => scount~14.OUTPUTSELECT
clear => scount~15.OUTPUTSELECT
clear => scount~16.OUTPUTSELECT
clear => scount~17.OUTPUTSELECT
clear => scount~18.OUTPUTSELECT
clear => scount~19.OUTPUTSELECT
clear => scount~20.OUTPUTSELECT
clear => scount~21.OUTPUTSELECT
clear => scount~22.OUTPUTSELECT
clear => scount~23.OUTPUTSELECT
clear => scount~24.OUTPUTSELECT
clear => scount~25.OUTPUTSELECT
clear => scount~26.OUTPUTSELECT
clear => cntm~18.OUTPUTSELECT
clear => cntm~19.OUTPUTSELECT
clear => cntm~20.OUTPUTSELECT
clear => cntm~21.OUTPUTSELECT
clear => cntm~22.OUTPUTSELECT
clear => cntm~23.OUTPUTSELECT
clear => cntm~24.OUTPUTSELECT
clear => cntm~25.OUTPUTSELECT
clear => cntm~26.OUTPUTSELECT
clear => dbnc~1.IN0
clear => stks~1.OUTPUTSELECT
clear => stks~2.OUTPUTSELECT
clear => stks~3.OUTPUTSELECT
clear => stks~4.OUTPUTSELECT
clear => ssk~0.OUTPUTSELECT
clear => ssk~1.OUTPUTSELECT
clear => dbnc.ENA
clear => r_w~reg0.ENA
clear => en~reg0.ENA
prom_data[0] => Mux~13.IN10
prom_data[1] => Mux~12.IN10
prom_data[2] => Mux~11.IN10
prom_data[3] => Mux~10.IN10
prom_data[4] => Mux~9.IN10
prom_data[5] => Mux~8.IN10
prom_data[6] => Mux~7.IN10
prom_data[7] => Mux~6.IN10
prom_data[8] => process3~1.IN1
sel[0] => clkm.IN1
sel[1] => clkm.IN0
en <= en~reg0.DB_MAX_OUTPUT_PORT_TYPE
r_w <= r_w~reg0.DB_MAX_OUTPUT_PORT_TYPE
d_i <= d_i~reg0.DB_MAX_OUTPUT_PORT_TYPE
promadr[0] <= promadr~15.DB_MAX_OUTPUT_PORT_TYPE
promadr[1] <= promadr~14.DB_MAX_OUTPUT_PORT_TYPE
promadr[2] <= promadr~13.DB_MAX_OUTPUT_PORT_TYPE
promadr[3] <= promadr~12.DB_MAX_OUTPUT_PORT_TYPE
promadr[4] <= promadr~11.DB_MAX_OUTPUT_PORT_TYPE
promadr[5] <= promadr~10.DB_MAX_OUTPUT_PORT_TYPE
promadr[6] <= promadr~9.DB_MAX_OUTPUT_PORT_TYPE
promadr[7] <= promadr~8.DB_MAX_OUTPUT_PORT_TYPE
db[0] <= db[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[1] <= db[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[2] <= db[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[3] <= db[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[4] <= db[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[5] <= db[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[6] <= db[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
db[7] <= db[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|lcdmddr|pprom6x8:inst2
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]


|lcdmddr|pprom6x8:inst2|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_gkq:auto_generated.address_a[0]
address_a[1] => altsyncram_gkq:auto_generated.address_a[1]
address_a[2] => altsyncram_gkq:auto_generated.address_a[2]
address_a[3] => altsyncram_gkq:auto_generated.address_a[3]
address_a[4] => altsyncram_gkq:auto_generated.address_a[4]
address_a[5] => altsyncram_gkq:auto_generated.address_a[5]
address_a[6] => altsyncram_gkq:auto_generated.address_a[6]
address_a[7] => altsyncram_gkq:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_gkq:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_gkq:auto_generated.q_a[0]
q_a[1] <= altsyncram_gkq:auto_generated.q_a[1]
q_a[2] <= altsyncram_gkq:auto_generated.q_a[2]
q_a[3] <= altsyncram_gkq:auto_generated.q_a[3]
q_a[4] <= altsyncram_gkq:auto_generated.q_a[4]
q_a[5] <= altsyncram_gkq:auto_generated.q_a[5]
q_a[6] <= altsyncram_gkq:auto_generated.q_a[6]
q_a[7] <= altsyncram_gkq:auto_generated.q_a[7]
q_a[8] <= altsyncram_gkq:auto_generated.q_a[8]
q_b[0] <= <UNC>


|lcdmddr|pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT