lcdmddr.tan.qmsg

128×64单色点阵LCD的quartus工程文件

{ "Info" "ITDB_TSU_RESULT" "lcdmpddr:inst\|stks\[3\] clear sclk 6.113 ns register " "Info: tsu for register lcdmpddr:inst\|stks\[3\] (data pin = clear, clock pin = sclk) is 6.113 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.885 ns + Longest pin register " "Info: + Longest pin to register delay is 13.885 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clear 1 PIN PIN_16 38 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 38; PIN Node = 'clear'" {  } { { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" "" "" { Report "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/lcdmddr_cmp.qrpt" Compiler "lcdmddr" "UNKNOWN" "V1" "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/lcdmddr.quartus_db" { Floorplan "" "" "" { clear } "NODE_NAME" } } } { "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmddr/lcdmddr.bdf" "" "" { Schematic "F:/KH-310&& CiC-310/KH-310/实验程序/EP1C6/08 lcdmd