pprom6c8.tan.rpt

128×64单色点阵LCD的quartus工程文件

; N/A   ; None         ; 12.477 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 ; q[6] ; clkadr     ;
; N/A   ; None         ; 12.477 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg6 ; q[6] ; clkadr     ;
; N/A   ; None         ; 12.465 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 ; q[4] ; clkadr     ;
; N/A   ; None         ; 12.465 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 ; q[4] ; clkadr     ;
; N/A   ; None         ; 12.465 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg2 ; q[4] ; clkadr     ;
; N/A   ; None         ; 12.465 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg3 ; q[4] ; clkadr     ;
; N/A   ; None         ; 12.465 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg4 ; q[4] ; clkadr     ;
; N/A   ; None         ; 12.465 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 ; q[4] ; clkadr     ;
; N/A   ; None         ; 12.465 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg6 ; q[4] ; clkadr     ;
; N/A   ; None         ; 12.134 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 ; q[1] ; clkadr     ;
; N/A   ; None         ; 12.134 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 ; q[1] ; clkadr     ;
; N/A   ; None         ; 12.134 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg2 ; q[1] ; clkadr     ;
; N/A   ; None         ; 12.134 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg3 ; q[1] ; clkadr     ;
; N/A   ; None         ; 12.134 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg4 ; q[1] ; clkadr     ;
; N/A   ; None         ; 12.134 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 ; q[1] ; clkadr     ;
; N/A   ; None         ; 12.134 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg6 ; q[1] ; clkadr     ;
; N/A   ; None         ; 12.117 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 ; q[7] ; clkadr     ;
; N/A   ; None         ; 12.117 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 ; q[7] ; clkadr     ;
; N/A   ; None         ; 12.117 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg2 ; q[7] ; clkadr     ;
; N/A   ; None         ; 12.117 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg3 ; q[7] ; clkadr     ;
; N/A   ; None         ; 12.117 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg4 ; q[7] ; clkadr     ;
; N/A   ; None         ; 12.117 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 ; q[7] ; clkadr     ;
; N/A   ; None         ; 12.117 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg6 ; q[7] ; clkadr     ;
; N/A   ; None         ; 11.825 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 ; q[0] ; clkadr     ;
; N/A   ; None         ; 11.825 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 ; q[0] ; clkadr     ;
; N/A   ; None         ; 11.825 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg2 ; q[0] ; clkadr     ;
; N/A   ; None         ; 11.825 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg3 ; q[0] ; clkadr     ;
; N/A   ; None         ; 11.825 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg4 ; q[0] ; clkadr     ;
; N/A   ; None         ; 11.825 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 ; q[0] ; clkadr     ;
; N/A   ; None         ; 11.825 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg6 ; q[0] ; clkadr     ;
; N/A   ; None         ; 11.824 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 ; q[3] ; clkadr     ;
; N/A   ; None         ; 11.824 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 ; q[3] ; clkadr     ;
; N/A   ; None         ; 11.824 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg2 ; q[3] ; clkadr     ;
; N/A   ; None         ; 11.824 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg3 ; q[3] ; clkadr     ;
; N/A   ; None         ; 11.824 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg4 ; q[3] ; clkadr     ;
; N/A   ; None         ; 11.824 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 ; q[3] ; clkadr     ;
; N/A   ; None         ; 11.824 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg6 ; q[3] ; clkadr     ;
; N/A   ; None         ; 11.817 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 ; q[2] ; clkadr     ;
; N/A   ; None         ; 11.817 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 ; q[2] ; clkadr     ;
; N/A   ; None         ; 11.817 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg2 ; q[2] ; clkadr     ;
; N/A   ; None         ; 11.817 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg3 ; q[2] ; clkadr     ;
; N/A   ; None         ; 11.817 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg4 ; q[2] ; clkadr     ;
; N/A   ; None         ; 11.817 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 ; q[2] ; clkadr     ;
; N/A   ; None         ; 11.817 ns  ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg6 ; q[2] ; clkadr     ;
+-------+--------------+------------+-------------------------------------------------------------------------------------------------------------+------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                        ;
+---------------+-------------+-----------+--------+-------------------------------------------------------------------------------------------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                                                                                                          ; To Clock ;
+---------------+-------------+-----------+--------+-------------------------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; -4.106 ns ; adr[5] ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 ; clkadr   ;
; N/A           ; None        ; -4.420 ns ; adr[3] ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg3 ; clkadr   ;
; N/A           ; None        ; -4.427 ns ; adr[2] ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg2 ; clkadr   ;
; N/A           ; None        ; -4.442 ns ; adr[4] ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg4 ; clkadr   ;
; N/A           ; None        ; -4.469 ns ; adr[0] ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 ; clkadr   ;
; N/A           ; None        ; -4.583 ns ; adr[6] ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg6 ; clkadr   ;
; N/A           ; None        ; -4.767 ns ; adr[1] ; pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 ; clkadr   ;
+---------------+-------------+-----------+--------+-------------------------------------------------------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Fri Oct 28 07:09:00 2005
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pprom6c8 -c pprom6c8 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkadr" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clkadr"
Info: tsu for memory "pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1" (data pin = "adr[1]", clock pin = "clkadr") is 4.915 ns
    Info: + Longest pin to memory delay is 8.078 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_226; Fanout = 1; PIN Node = 'adr[1]'
        Info: 2: + IC(6.220 ns) + CELL(0.383 ns) = 8.078 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1'
        Info: Total cell delay = 1.858 ns ( 23.00 % )
        Info: Total interconnect delay = 6.220 ns ( 77.00 % )
    Info: + Micro setup delay of destination is 0.093 ns
    Info: - Shortest clock path from clock "clkadr" to destination memory is 3.256 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'clkadr'
        Info: 2: + IC(1.065 ns) + CELL(0.722 ns) = 3.256 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1'
        Info: Total cell delay = 2.191 ns ( 67.29 % )
        Info: Total interconnect delay = 1.065 ns ( 32.71 % )
Info: tco from clock "clkadr" to destination pin "q[5]" through memory "pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0" is 12.492 ns
    Info: + Longest clock path from clock "clkadr" to source memory is 3.256 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'clkadr'
        Info: 2: + IC(1.065 ns) + CELL(0.722 ns) = 3.256 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0'
        Info: Total cell delay = 2.191 ns ( 67.29 % )
        Info: Total interconnect delay = 1.065 ns ( 32.71 % )
    Info: + Micro clock to output delay of source is 0.650 ns
    Info: + Longest memory to pin delay is 8.586 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X19_Y26; Fanout = 1; MEM Node = 'pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[5]'
        Info: 3: + IC(2.170 ns) + CELL(2.108 ns) = 8.586 ns; Loc. = PIN_203; Fanout = 0; PIN Node = 'q[5]'
        Info: Total cell delay = 6.416 ns ( 74.73 % )
        Info: Total interconnect delay = 2.170 ns ( 25.27 % )
Info: th for memory "pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5" (data pin = "adr[5]", clock pin = "clkadr") is -4.106 ns
    Info: + Longest clock path from clock "clkadr" to destination memory is 3.256 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'clkadr'
        Info: 2: + IC(1.065 ns) + CELL(0.722 ns) = 3.256 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5'
        Info: Total cell delay = 2.191 ns ( 67.29 % )
        Info: Total interconnect delay = 1.065 ns ( 32.71 % )
    Info: + Micro hold delay of destination is 0.055 ns
    Info: - Shortest pin to memory delay is 7.417 ns
        Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_216; Fanout = 1; PIN Node = 'adr[5]'
        Info: 2: + IC(5.559 ns) + CELL(0.383 ns) = 7.417 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5'
        Info: Total cell delay = 1.858 ns ( 25.05 % )
        Info: Total interconnect delay = 5.559 ns ( 74.95 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Oct 28 07:09:01 2005
    Info: Elapsed time: 00:00:02