pprom6c8.map.qmsg

128×64单色点阵LCD的quartus工程文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 28 07:08:40 2005 " "Info: Processing started: Fri Oct 28 07:08:40 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pprom6c8 -c pprom6c8 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pprom6c8 -c pprom6c8" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pprom6c8.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pprom6c8.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pprom6c8 " "Info: Found entity 1: pprom6c8" {  } { { "pprom6c8.bdf" "" { Schematic "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6c8.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pprom6c8 " "Info: Elaborating entity \"pprom6c8\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "pprom6x8.vhd 2 1 " "Info: Using design file pprom6x8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pprom6x8-SYN " "Info: Found design unit 1: pprom6x8-SYN" {  } { { "pprom6x8.vhd" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6x8.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 pprom6x8 " "Info: Found entity 1: pprom6x8" {  } { { "pprom6x8.vhd" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6x8.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pprom6x8 pprom6x8:inst " "Info: Elaborating entity \"pprom6x8\" for hierarchy \"pprom6x8:inst\"" {  } { { "pprom6c8.bdf" "inst" { Schematic "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6c8.bdf" { { 56 256 416 136 "inst" "" } } } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram pprom6x8:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"pprom6x8:inst\|altsyncram:altsyncram_component\"" {  } { { "pprom6x8.vhd" "altsyncram_component" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6x8.vhd" 80 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_t0t.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_t0t.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_t0t " "Info: Found entity 1: altsyncram_t0t" {  } { { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_t0t pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated " "Info: Elaborating entity \"altsyncram_t0t\" for hierarchy \"pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Warning" "WCDB_CDB_LESS_INI_CONTENT" "128 64 " "Warning: Memory depth value (128) in design file differs from memory depth value (64) in Memory Initialization File -- setting initial value for remaining addresses to 0" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "24 " "Info: Implemented 24 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "8 " "Info: Implemented 8 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 07:08:44 2005 " "Info: Processing ended: Fri Oct 28 07:08:44 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}