📄 pprom6c8.tan.qmsg
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{ "Info" "ITDB_TSU_RESULT" "pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg1 adr\[1\] clkadr 4.915 ns memory " "Info: tsu for memory \"pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg1\" (data pin = \"adr\[1\]\", clock pin = \"clkadr\") is 4.915 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.078 ns + Longest pin memory " "Info: + Longest pin to memory delay is 8.078 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns adr\[1\] 1 PIN PIN_226 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_226; Fanout = 1; PIN Node = 'adr\[1\]'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "" { adr[1] } "NODE_NAME" } "" } } { "pprom6c8.bdf" "" { Schematic "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6c8.bdf" { { 80 48 216 96 "adr\[6..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.220 ns) + CELL(0.383 ns) 8.078 ns pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg1 2 MEM M4K_X19_Y26 8 " "Info: 2: + IC(6.220 ns) + CELL(0.383 ns) = 8.078 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg1'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "6.603 ns" { adr[1] pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 174 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.858 ns 23.00 % " "Info: Total cell delay = 1.858 ns ( 23.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.220 ns 77.00 % " "Info: Total interconnect delay = 6.220 ns ( 77.00 % )" { } { } 0} } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "8.078 ns" { adr[1] pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.078 ns" { adr[1] adr[1]~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } { 0.000ns 0.000ns 6.220ns } { 0.000ns 1.475ns 0.383ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" { } { { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 174 2 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkadr destination 3.256 ns - Shortest memory " "Info: - Shortest clock path from clock \"clkadr\" to destination memory is 3.256 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkadr 1 CLK PIN_29 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'clkadr'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "" { clkadr } "NODE_NAME" } "" } } { "pprom6c8.bdf" "" { Schematic "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6c8.bdf" { { 96 48 216 112 "clkadr" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.722 ns) 3.256 ns pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg1 2 MEM M4K_X19_Y26 8 " "Info: 2: + IC(1.065 ns) + CELL(0.722 ns) = 3.256 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg1'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "1.787 ns" { clkadr pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } "NODE_NAME" } "" } } { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 174 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 67.29 % " "Info: Total cell delay = 2.191 ns ( 67.29 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns 32.71 % " "Info: Total interconnect delay = 1.065 ns ( 32.71 % )" { } { } 0} } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "3.256 ns" { clkadr pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.256 ns" { clkadr clkadr~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.722ns } } } } 0} } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "8.078 ns" { adr[1] pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.078 ns" { adr[1] adr[1]~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } { 0.000ns 0.000ns 6.220ns } { 0.000ns 1.475ns 0.383ns } } } { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "3.256 ns" { clkadr pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.256 ns" { clkadr clkadr~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg1 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.722ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkadr q\[5\] pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg0 12.492 ns memory " "Info: tco from clock \"clkadr\" to destination pin \"q\[5\]\" through memory \"pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg0\" is 12.492 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkadr source 3.256 ns + Longest memory " "Info: + Longest clock path from clock \"clkadr\" to source memory is 3.256 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkadr 1 CLK PIN_29 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'clkadr'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "" { clkadr } "NODE_NAME" } "" } } { "pprom6c8.bdf" "" { Schematic "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6c8.bdf" { { 96 48 216 112 "clkadr" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.722 ns) 3.256 ns pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg0 2 MEM M4K_X19_Y26 8 " "Info: 2: + IC(1.065 ns) + CELL(0.722 ns) = 3.256 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg0'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "1.787 ns" { clkadr pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 174 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 67.29 % " "Info: Total cell delay = 2.191 ns ( 67.29 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns 32.71 % " "Info: Total interconnect delay = 1.065 ns ( 32.71 % )" { } { } 0} } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "3.256 ns" { clkadr pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.256 ns" { clkadr clkadr~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.722ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" { } { { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 174 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.586 ns + Longest memory pin " "Info: + Longest memory to pin delay is 8.586 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg0 1 MEM M4K_X19_Y26 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg0'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "" { pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 174 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|q_a\[5\] 2 MEM M4K_X19_Y26 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X19_Y26; Fanout = 1; MEM Node = 'pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|q_a\[5\]'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "4.308 ns" { pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[5] } "NODE_NAME" } "" } } { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 38 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.170 ns) + CELL(2.108 ns) 8.586 ns q\[5\] 3 PIN PIN_203 0 " "Info: 3: + IC(2.170 ns) + CELL(2.108 ns) = 8.586 ns; Loc. = PIN_203; Fanout = 0; PIN Node = 'q\[5\]'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "4.278 ns" { pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[5] q[5] } "NODE_NAME" } "" } } { "pprom6c8.bdf" "" { Schematic "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6c8.bdf" { { 88 448 624 104 "q\[7..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.416 ns 74.73 % " "Info: Total cell delay = 6.416 ns ( 74.73 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.170 ns 25.27 % " "Info: Total interconnect delay = 2.170 ns ( 25.27 % )" { } { } 0} } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "8.586 ns" { pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[5] q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.586 ns" { pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[5] q[5] } { 0.000ns 0.000ns 2.170ns } { 0.000ns 4.308ns 2.108ns } } } } 0} } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "3.256 ns" { clkadr pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.256 ns" { clkadr clkadr~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.722ns } } } { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "8.586 ns" { pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[5] q[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.586 ns" { pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|q_a[5] q[5] } { 0.000ns 0.000ns 2.170ns } { 0.000ns 4.308ns 2.108ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg5 adr\[5\] clkadr -4.106 ns memory " "Info: th for memory \"pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg5\" (data pin = \"adr\[5\]\", clock pin = \"clkadr\") is -4.106 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkadr destination 3.256 ns + Longest memory " "Info: + Longest clock path from clock \"clkadr\" to destination memory is 3.256 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkadr 1 CLK PIN_29 7 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 7; CLK Node = 'clkadr'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "" { clkadr } "NODE_NAME" } "" } } { "pprom6c8.bdf" "" { Schematic "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6c8.bdf" { { 96 48 216 112 "clkadr" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.065 ns) + CELL(0.722 ns) 3.256 ns pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg5 2 MEM M4K_X19_Y26 8 " "Info: 2: + IC(1.065 ns) + CELL(0.722 ns) = 3.256 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg5'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "1.787 ns" { clkadr pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 174 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 67.29 % " "Info: Total cell delay = 2.191 ns ( 67.29 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.065 ns 32.71 % " "Info: Total interconnect delay = 1.065 ns ( 32.71 % )" { } { } 0} } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "3.256 ns" { clkadr pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.256 ns" { clkadr clkadr~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.722ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.055 ns + " "Info: + Micro hold delay of destination is 0.055 ns" { } { { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 174 2 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.417 ns - Shortest pin memory " "Info: - Shortest pin to memory delay is 7.417 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns adr\[5\] 1 PIN PIN_216 1 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_216; Fanout = 1; PIN Node = 'adr\[5\]'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "" { adr[5] } "NODE_NAME" } "" } } { "pprom6c8.bdf" "" { Schematic "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/pprom6c8.bdf" { { 80 48 216 96 "adr\[6..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.559 ns) + CELL(0.383 ns) 7.417 ns pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg5 2 MEM M4K_X19_Y26 8 " "Info: 2: + IC(5.559 ns) + CELL(0.383 ns) = 7.417 ns; Loc. = M4K_X19_Y26; Fanout = 8; MEM Node = 'pprom6x8:inst\|altsyncram:altsyncram_component\|altsyncram_t0t:auto_generated\|ram_block1a7~porta_address_reg5'" { } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "5.942 ns" { adr[5] pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "db/altsyncram_t0t.tdf" "" { Text "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/altsyncram_t0t.tdf" 174 2 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.858 ns 25.05 % " "Info: Total cell delay = 1.858 ns ( 25.05 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.559 ns 74.95 % " "Info: Total interconnect delay = 5.559 ns ( 74.95 % )" { } { } 0} } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "7.417 ns" { adr[5] pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.417 ns" { adr[5] adr[5]~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 0.000ns 5.559ns } { 0.000ns 1.475ns 0.383ns } } } } 0} } { { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "3.256 ns" { clkadr pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.256 ns" { clkadr clkadr~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 0.000ns 1.065ns } { 0.000ns 1.469ns 0.722ns } } } { "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" "" { Report "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8_cmp.qrpt" Compiler "pprom6c8" "UNKNOWN" "V1" "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/db/pprom6c8.quartus_db" { Floorplan "C:/ddata/qutvhd/ep1c12/lcdmdr/pprom6x8/" "" "7.417 ns" { adr[5] pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.417 ns" { adr[5] adr[5]~out0 pprom6x8:inst|altsyncram:altsyncram_component|altsyncram_t0t:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 0.000ns 5.559ns } { 0.000ns 1.475ns 0.383ns } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 28 07:09:01 2005 " "Info: Processing ended: Fri Oct 28 07:09:01 2005" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0} } { } 0}
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