lcdmddr.map.rpt

128×64单色点阵LCD的quartus工程文件

+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 31    ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 6     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
lcdmddr
 |-- lcdmpddr:inst
      |-- lpm_counter:cntm_rtl_0
           |-- cntr_sv7:auto_generated
      |-- lpm_counter:scount_rtl_1
           |-- cntr_lc7:auto_generated
 |-- pprom6x8:inst2
      |-- altsyncram:altsyncram_component
           |-- altsyncram_gkq:auto_generated


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                       ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------+
; Compilation Hierarchy Node               ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                                                   ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------+
; |lcdmddr                                 ; 88 (0)      ; 52           ; 2304        ; 16   ; 0            ; 36 (0)       ; 3 (0)             ; 49 (0)           ; 31 (0)          ; |lcdmddr                                                                              ;
;    |lcdmpddr:inst|                       ; 88 (57)     ; 52           ; 0           ; 0    ; 0            ; 36 (36)      ; 3 (3)             ; 49 (18)          ; 31 (0)          ; |lcdmddr|lcdmpddr:inst                                                                ;
;       |lpm_counter:cntm_rtl_0|           ; 9 (0)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (0)            ; 9 (0)           ; |lcdmddr|lcdmpddr:inst|lpm_counter:cntm_rtl_0                                         ;
;          |cntr_sv7:auto_generated|       ; 9 (9)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 9 (9)           ; |lcdmddr|lcdmpddr:inst|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated                 ;
;       |lpm_counter:scount_rtl_1|         ; 22 (0)      ; 22           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 22 (0)           ; 22 (0)          ; |lcdmddr|lcdmpddr:inst|lpm_counter:scount_rtl_1                                       ;
;          |cntr_lc7:auto_generated|       ; 22 (22)     ; 22           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 22 (22)          ; 22 (22)         ; |lcdmddr|lcdmpddr:inst|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated               ;
;    |pprom6x8:inst2|                      ; 0 (0)       ; 0            ; 2304        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |lcdmddr|pprom6x8:inst2                                                               ;
;       |altsyncram:altsyncram_component|  ; 0 (0)       ; 0            ; 2304        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |lcdmddr|pprom6x8:inst2|altsyncram:altsyncram_component                               ;
;          |altsyncram_gkq:auto_generated| ; 0 (0)       ; 0            ; 2304        ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |lcdmddr|pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated ;
+------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/lcdmddr.map.eqn.


+-----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                        ;
+-----------------------------------------------------------------------------+-----------------+
; File Name                                                                   ; Used in Netlist ;
+-----------------------------------------------------------------------------+-----------------+
; lcdmpddr/lcdmpddr.vhd                                                       ; yes             ;
; pprom6x8/pprom6x8.vhd                                                       ; yes             ;
; lcdmddr.bdf                                                                 ; yes             ;
; g:/quartus41/libraries/megafunctions/altsyncram.tdf                         ; yes             ;
; g:/quartus41/libraries/megafunctions/stratix_ram_block.inc                  ; yes             ;
; F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/altsyncram_gkq.tdf ; yes             ;
; g:/quartus41/libraries/megafunctions/lpm_counter.tdf                        ; yes             ;
; g:/quartus41/libraries/megafunctions/lpm_constant.inc                       ; yes             ;
; F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/cntr_sv7.tdf       ; yes             ;
; F:/KH-310&& CiC-310/KH-310/实验程序/EP1C12/08 lcdmddr/db/cntr_lc7.tdf       ; yes             ;
+-----------------------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 88      ;
; Total combinational functions     ; 85      ;
; Total 4-input functions           ; 25      ;
; Total 3-input functions           ; 13      ;
; Total 2-input functions           ; 24      ;
; Total 1-input functions           ; 23      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 52      ;
; Total logic cells in carry chains ; 31      ;
; I/O pins                          ; 16      ;
; Total memory bits                 ; 2304    ;
; Maximum fan-out node              ; clear   ;
; Maximum fan-out                   ; 38      ;
; Total fan-out                     ; 435     ;
; Average fan-out                   ; 3.85    ;
+-----------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                      ;
+-----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------+
; Name                                                                                    ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF        ;
+-----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------+
; pprom6x8:inst2|altsyncram:altsyncram_component|altsyncram_gkq:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 256          ; 9            ; --           ; --           ; 2304 ; lcdmcp.mif ;
+-----------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Thu Jul 13 14:21:21 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off lcdmddr -c lcdmddr
Info: Found 2 design units, including 1 entities, in source file lcdmpddr/lcdmpddr.vhd
    Info: Found design unit 1: lcdmpddr-lcdmpddr_arch
    Info: Found entity 1: lcdmpddr
Info: Found 2 design units, including 1 entities, in source file pprom6x8/pprom6x8.vhd
    Info: Found design unit 1: pprom6x8-SYN
    Info: Found entity 1: pprom6x8
Info: Found 1 design units, including 1 entities, in source file lcdmddr.bdf
    Info: Found entity 1: lcdmddr
Warning: VHDL Process Statement warning at lcdmpddr.vhd(41): signal scount is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at lcdmpddr.vhd(42): signal scount is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at lcdmpddr.vhd(43): signal scount is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at lcdmpddr.vhd(44): signal scount is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at lcdmpddr.vhd(95): OTHERS choice is never selected
Info: Found 1 design units, including 1 entities, in source file g:/quartus41/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_gkq.tdf
    Info: Found entity 1: altsyncram_gkq
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: lcdmpddr:inst|cntm[0]~63
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=27) from the following logic: lcdmpddr:inst|scount[0]~27
Info: Found 1 design units, including 1 entities, in source file g:/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_sv7.tdf
    Info: Found entity 1: cntr_sv7
Info: Found 1 design units, including 1 entities, in source file db/cntr_lc7.tdf
    Info: Found entity 1: cntr_lc7
Info: Implemented 113 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 11 output pins
    Info: Implemented 88 logic cells
    Info: Implemented 9 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Thu Jul 13 14:21:29 2006
    Info: Elapsed time: 00:00:07