lcdmpddr.tan.rpt

128×64单色点阵LCD的quartus工程文件

; Device name                                           ; EP1C12Q240C8       ;      ;    ;
; Timing Models                                         ; Production         ;      ;    ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                    ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-------------------------------------------------------------+------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                                    ; From                                                        ; To                                                         ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-------------------------------------------------------------+------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; 6.025 ns                                       ; clear                                                       ; lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[1] ;            ; sclk     ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 18.232 ns                                      ; lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[4]    ; promadr[1]                                                 ; sclk       ;          ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 2.003 ns                                       ; sel[1]                                                      ; d[0]                                                       ;            ; sclk     ; 0            ;
; Worst-case Minimum tco       ; N/A                                      ; None          ; 11.491 ns                                      ; db[1]~reg0                                                  ; db[1]                                                      ; sclk       ;          ; 0            ;
; Clock Setup: 'sclk'          ; N/A                                      ; None          ; 206.23 MHz ( period = 4.849 ns )               ; lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[4]    ; en~reg0                                                    ; sclk       ; sclk     ; 0            ;
; Clock Setup: 'sel[0]'        ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[1]    ; lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[7]   ; sel[0]     ; sel[0]   ; 0            ;
; Clock Setup: 'sel[1]'        ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[1]    ; lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[7]   ; sel[1]     ; sel[1]   ; 0            ;
; Clock Setup: 'sclkm'         ; N/A                                      ; None          ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[1]    ; lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[7]   ; sclkm      ; sclkm    ; 0            ;
; Clock Hold: 'sclk'           ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; lpm_counter:scount_rtl_1|cntr_lc7:auto_generated|safe_q[21] ; d[0]                                                       ; sclk       ; sclk     ; 3            ;
; Total number of failed paths ;                                          ;               ;                                                ;                                                             ;                                                            ;            ;          ; 3            ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-------------------------------------------------------------+------------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; sclk            ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; sclkm           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; sel[1]          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; sel[0]          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'sclk'                                                                                                                                                                                                                                                                                                                   ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                        ; To                                                          ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 206.23 MHz ( period = 4.849 ns )                    ; lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated|safe_q[4]    ; en~reg0                                                     ; sclk       ; sclk     ; None                        ; None                      ; None                    ;