lcdmpddr.map.rpt

128×64单色点阵LCD的quartus工程文件

; Number of synthesis-generated cells                    ; 61    ;
; Number of WYSIWYG LUTs                                 ; 37    ;
; Number of synthesis-generated LUTs                     ; 58    ;
; Number of WYSIWYG registers                            ; 37    ;
; Number of synthesis-generated registers                ; 23    ;
; Number of cells with combinational logic only          ; 38    ;
; Number of cells with registers only                    ; 3     ;
; Number of cells with combinational logic and registers ; 57    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 31    ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 7     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
lcdmpddr
 |-- lpm_counter:cntm_rtl_0
      |-- cntr_sv7:auto_generated
 |-- lpm_counter:scount_rtl_1
      |-- cntr_lc7:auto_generated


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                   ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------+
; Compilation Hierarchy Node      ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name                                        ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------+
; |lcdmpddr                       ; 98 (67)     ; 60           ; 0           ; 45   ; 0            ; 38 (38)      ; 3 (3)             ; 57 (26)          ; 31 (0)          ; |lcdmpddr                                                  ;
;    |lpm_counter:cntm_rtl_0|     ; 9 (0)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (0)            ; 9 (0)           ; |lcdmpddr|lpm_counter:cntm_rtl_0                           ;
;       |cntr_sv7:auto_generated| ; 9 (9)       ; 9            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 9 (9)            ; 9 (9)           ; |lcdmpddr|lpm_counter:cntm_rtl_0|cntr_sv7:auto_generated   ;
;    |lpm_counter:scount_rtl_1|   ; 22 (0)      ; 22           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 22 (0)           ; 22 (0)          ; |lcdmpddr|lpm_counter:scount_rtl_1                         ;
;       |cntr_lc7:auto_generated| ; 22 (22)     ; 22           ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 22 (22)          ; 22 (22)         ; |lcdmpddr|lpm_counter:scount_rtl_1|cntr_lc7:auto_generated ;
+---------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/TEMP/310exp_h/lcdmpddr/lcdmpddr.map.eqn.


+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                       ;
+----------------------------------------------------------------------------+-----------------+
; File Name                                                                  ; Used in Netlist ;
+----------------------------------------------------------------------------+-----------------+
; lcdmpddr.vhd                                                               ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/lpm_counter.tdf  ; yes             ;
; d:/program files/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes             ;
; C:/TEMP/310exp_h/lcdmpddr/db/cntr_sv7.tdf                                  ; yes             ;
; C:/TEMP/310exp_h/lcdmpddr/db/cntr_lc7.tdf                                  ; yes             ;
+----------------------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 98      ;
; Total combinational functions     ; 95      ;
; Total 4-input functions           ; 35      ;
; Total 3-input functions           ; 17      ;
; Total 2-input functions           ; 20      ;
; Total 1-input functions           ; 23      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 60      ;
; Total logic cells in carry chains ; 31      ;
; I/O pins                          ; 45      ;
; Maximum fan-out node              ; clear   ;
; Maximum fan-out                   ; 46      ;
; Total fan-out                     ; 416     ;
; Average fan-out                   ; 2.91    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sat Dec 03 17:53:38 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off lcdmpddr -c lcdmpddr
Info: Found 2 design units, including 1 entities, in source file lcdmpddr.vhd
    Info: Found design unit 1: lcdmpddr-lcdmpddr_arch
    Info: Found entity 1: lcdmpddr
Warning: VHDL Process Statement warning at lcdmpddr.vhd(32): signal sclk is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at lcdmpddr.vhd(42): signal scount is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at lcdmpddr.vhd(43): signal scount is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at lcdmpddr.vhd(44): signal scount is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at lcdmpddr.vhd(45): signal sclkm is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at lcdmpddr.vhd(62): signal clkm is in statement, but is not in sensitivity list
Info: VHDL Case Statement information at lcdmpddr.vhd(104): OTHERS choice is never selected
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=9) from the following logic: cntm[0]~63
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=27) from the following logic: scount[0]~27
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_sv7.tdf
    Info: Found entity 1: cntr_sv7
Info: Found 1 design units, including 1 entities, in source file db/cntr_lc7.tdf
    Info: Found entity 1: cntr_lc7
Info: Implemented 143 device resources after synthesis - the final resource count might be different
    Info: Implemented 25 input pins
    Info: Implemented 20 output pins
    Info: Implemented 98 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
    Info: Processing ended: Sat Dec 03 17:53:43 2005
    Info: Elapsed time: 00:00:05