wprounit_ap.v

hmac的verilog代码, 通过控制字选择进行sha1运算或hmac运算

///////////////////////////////////////////////////////
//    module describe
// name: 		wprounit
// function:	produce wt[79:0]
// writer:		zy
// data:		2006/02/27
// version:		1.0
// feature:		
////////////////////////////////////////////////////////



module wprounit(clk,reset,datain,dataready,wtk,wtready);

input clk;
input reset;
input [511:0] datain;
input dataready;

output [31:0] wtk;
output wtready;

reg [511:0] iwt;
reg [511:0] iwttmp;
reg [31:0] wt;
reg [31:0] wtk;
reg [4:0] intercnt;//0~19
reg [4:0] intercnttmp;
reg [1:0] roundcnt;//0~3
reg [1:0] roundcnttmp;
reg [31:0] xorwt;
reg wprend;
reg wprendtmp;
reg wtready;
reg [31:0] ki;

parameter k0=32'h5a827999;
parameter k1=32'h6ed9eba1;
parameter k2=32'h8f1bbcdc;
parameter k3=32'hca62c1d6;

wire [31:0] wtkresult;

claa_32b claa_32_0(wt,ki,wtkresult);

always @(posedge clk)

begin
	if (reset)
		begin
			iwt <=0;
			intercnt <=0;
			roundcnt <=0;
			wprend <=0;
		end
		
	else if (dataready)
		begin
			iwt <= datain;
			wprend <=0;
			intercnt <=0;
			roundcnt <=0;
		end
	else 
		begin	
			iwt <=iwttmp;
			intercnt <=intercnttmp;
			roundcnt <=roundcnttmp;
			wprend <=wprendtmp;
		end
end

always @(wprend or iwt)
begin
	if (wprend)
		xorwt <=0;
	else
		xorwt <= (iwt[511:480]^iwt[447:416]^iwt[255:224]^iwt[95:64]);
end

always @(intercnt or roundcnt or wprend or iwt or xorwt)
begin
	if ((roundcnt ==0)&&(!wprend)&&(intercnt<16))
				begin
					case (intercnt[3:0])
					0:			wt[31:0] <=iwt[511:480];																		
					1:			wt[31:0] <=iwt[479:448];																		
					2:			wt[31:0] <=iwt[447:416];																		
					3:			wt[31:0] <=iwt[415:384];																		
					4:			wt[31:0] <=iwt[383:352];																		
					5:			wt[31:0] <=iwt[351:320];																		
					6:			wt[31:0] <=iwt[319:288];																		
					7:			wt[31:0] <=iwt[287:256];																		
					8:			wt[31:0] <=iwt[255:224];																		
					9:			wt[31:0] <=iwt[223:192];																		
					10:			wt[31:0] <=iwt[191:160];																		
					11:			wt[31:0] <=iwt[159:128];																		
					12:			wt[31:0] <=iwt[127:96]; 																		
					13:			wt[31:0] <=iwt[95:64];  																		
					14:			wt[31:0] <=iwt[63:32];  																		
					default:	wt[31:0] <=iwt[31:0];   																		
					endcase
				end	
	else if (!wprend)
			wt<={xorwt[30:0],xorwt[31]};  
	else 
			wt<=0; 
		
end

always @(posedge clk)
begin
	if (reset)
		wtready<=0;
	else if (dataready)
		wtready<=1;
	else
		wtready<=0;
end

always @(roundcnt)
begin
		case(roundcnt)
			0:ki<=k0;
			1:ki<=k1;
			2:ki<=k2;
			3:ki<=k3;
		endcase
end

always @(posedge clk)
begin
	if (reset)
		wtk<=0;
	else
		wtk<=wtkresult;
end

always @(intercnt or roundcnt or wprend or iwt or wt)
begin
	if (((roundcnt!=0)&&(!wprend)&&(intercnt<20))||(roundcnt==0)&&(intercnt>15)&&(!wprend))
				begin
					iwttmp <= {iwt[479:0],wt[31:0]};
				end
	else 
		begin
			iwttmp <=iwt;
		end
end

always @(intercnt or roundcnt or wprend or iwt or xorwt or dataready)
begin
	if (dataready)
		begin
			intercnttmp<=0;
			roundcnttmp<=0;
			wprendtmp<=0;
		end
	else 
		begin
			if (intercnt==19)
		  		begin
		  			intercnttmp<=0;
		  			if (roundcnt==3)
		  				begin
		  					roundcnttmp<=0;
		  					wprendtmp <=1;
		  				end
		  			else 
		  				begin
		  					roundcnttmp<=roundcnt+1;
		  					wprendtmp<=wprend;
		  				end
		  		end
		  	else 
		  		begin 
					intercnttmp <=intercnt +1;
					roundcnttmp <=roundcnt;
					wprendtmp <=wprend;
				end
		end
end
endmodule