datapadunit.v

hmac的verilog代码, 通过控制字选择进行sha1运算或hmac运算

///////////////////////////////////////////////////////
//    				module describe
// name: 			datapadunit
// function:	data padding including keypad
// writer:		zy
// data:			2006/11/08
// version:		1.1
// feature:		the lenth of the message (by bits)  is 
//						not obligatory, but it must be the 
//						multiple of 8.
// address: 	0 - ctrl word
//						1 - keyin
//						2 - lengthin
//						3 - datain
//						4 - status
//						5-9 - digest out
//						15 - mask
////////////////////////////////////////////////////////


module datapadunit(en,clk,reset,wr,padflg,datain,addr,hashover,modsel,md1in,paddata,dataready,expadflgreg,lenerror,procsel,keyreadyreg,digestreadyreg);
//general input
input en,clk,reset,wr;
input [31:0] datain;
input [3:0]  addr;
//intermodule input
input padflg;
input hashover;
input modsel;
input [159:0] md1in;
//output
output [511:0] paddata;
output dataready;
output expadflgreg;
output lenerror;
output [1:0] procsel;
output keyreadyreg;
output digestreadyreg;

//for the output
reg [511:0] paddata;
reg dataready;
reg expadflgreg;
reg lenerror;
reg [1:0] procsel;
reg digestreadyreg;
//reg keyready;
 
//use for the module
reg [2:0] keycnt;
reg [3:0] datacnt;
reg [63:0] datalength;
reg [159:0] keyreg;
//reg lenerror;
reg keyreadyreg;
reg expadflg;
reg fulllengthreg;

reg [31:0] datatmp;

//ctrl signal
reg keyinc;
reg keycntclr;
reg datainc;
reg datacntclr;
reg ikeyready;
reg okeyready;
reg paddataready;
reg error;
reg md1ready;
reg resultready;
reg fulllength;
reg expadflgclr;

//use for the state machine
reg [4:0] currentstate;
reg [4:0] nextstate;

//state define
parameter idle = 0;
parameter rxkey = 1;
parameter sendikey = 2;
parameter waitiv1 = 3;
parameter sendokey = 4;
parameter waitiv2 = 5;
parameter rxlength = 6;
parameter rxdata = 7;
parameter datapad = 8;
parameter lengthpad = 9;
parameter senddata = 10;
parameter expad = 11;
parameter sendmd1 = 12;
parameter waitmd2 = 13;
parameter digestready = 14;
parameter lengtherror =15;
parameter hmackeyready = 16;

//parameter define
parameter ipad = 8'b00110110;
parameter opad = 8'b01011100;

//store the inputdata in the datatmp;
always @(posedge clk)
begin
	if (reset)
		datatmp <= 0;
	else if (en && ((addr == 1) || (addr == 2) || (addr == 3)))
		datatmp <= datain;
end
//expad reg
always @(posedge clk)
begin
	if (reset)
		expadflgreg <= 0;
	else if (expadflg)
		expadflgreg <= 1;
	else if (expadflgclr)
		expadflgreg <= 0;
end

//fulllength reg
always @(posedge clk)
begin
	if (reset)
		fulllengthreg <= 0;
	else if (fulllength)
		fulllengthreg <= 1;
	else if (resultready)
		fulllengthreg <= 0;
end

//lenerror reg
always @(posedge clk)
begin
	if (reset)
		lenerror <= 0;
	else
		lenerror <= error;
end
		
//count the key block
always @(posedge clk)
begin
	if (reset)
		keycnt <= 0;
	else if (keyinc)
		keycnt <= keycnt+1;
	else if (keycntclr)
		keycnt <= 0;
	else
		keycnt <= keycnt;
end

//count the data block
always @(posedge clk)
begin
	if (reset)
		datacnt <= 0;
	else if (datainc)
		datacnt <= datacnt+1;
	else if (datacntclr)
		datacnt <= 0;
	else
		datacnt <= datacnt;
end

//control dataready signal
always @(posedge clk)
begin
	if (reset)
		dataready <= 0;
	else if (ikeyready || okeyready || paddataready || md1ready)
		dataready <= 1;
	else
		dataready <=0;
end

//digestready reg
always @(posedge clk)
begin
	if (reset)
		digestreadyreg <= 0;
	else if (resultready)
		digestreadyreg <= 1;
	else if (en && wr && addr==9)
		digestreadyreg <= 0;
end

//state machine description

always @(posedge clk)
begin
	if (reset)
		currentstate <= idle;
	else
		currentstate <= nextstate;
end

always @(*)
begin	
	nextstate = idle;
	keyinc = 0;
	datainc = 0;
	ikeyready = 0;
	okeyready = 0;
	paddataready = 0;
	error = 0;
	md1ready = 0;
	resultready = 0;
	expadflg = 0;
	keycntclr = 0;
	datacntclr = 0;
	fulllength = 0;
	expadflgclr = 0;
	case (currentstate)
		idle:
			begin
				if (en && !wr && (addr == 1) && (modsel == 1))
					nextstate = rxkey;
				else if (en && !wr && (addr == 2) && !lenerror)
					nextstate = rxlength;
				else if (en && !wr && (addr == 3))
					nextstate = rxdata;
				else if (expadflgreg && hashover && padflg)
					nextstate = expad;
				else if (hashover && modsel && padflg)
					nextstate = sendmd1;
				else if (hashover && fulllengthreg)
					nextstate = expad;
				else if (hashover && ((!modsel && padflg && !expadflgreg) || (!padflg)))
					nextstate = digestready;
				else if ((!padflg && (datalength[8:0]!=0)) || (datalength[2:0] != 0))
					nextstate = lengtherror;
				else
					nextstate = idle;
			end
		rxkey:
			begin
				keyinc = 1;
				if (keycnt==4)
					begin
						nextstate = sendikey;
					end
				else if (en && !wr && (addr == 1))//in case of the writting operation followed clk by clk
					nextstate = rxkey;
				else 
					nextstate = idle;				
			end
		sendikey:
			begin
				ikeyready = 1;
				keycntclr = 1;
				nextstate = waitiv1;
			end
		waitiv1:
			begin
			keycntclr = 0;
			ikeyready = 0;
				if (hashover)
					begin
						nextstate = sendokey;
					end
				else
					nextstate = waitiv1;
			end
		sendokey:
			begin
				okeyready = 1;
				nextstate = waitiv2;
			end
		waitiv2:
			begin
				if (hashover)
					begin
						nextstate = hmackeyready;
					end
				else
					nextstate = waitiv2;
			end
		hmackeyready:
			begin
				nextstate = idle;
			end
		rxlength:
			begin
//				if((datain==0) && padflg)
//					nextstate = datapad;
//				else
					nextstate = idle;
			end
		rxdata:
			begin
				datainc =1;
				if (en && !wr && (addr == 3))
					nextstate = rxdata;
				else if ((datacnt==15) && !padflg)
					nextstate = senddata;
				else if (((datacnt == datalength[8:5]-1) && (datalength[4:3]==0) && padflg) || ((datacnt == datalength[8:5]) && (datalength[4:3]!=0  && padflg)))
					nextstate = datapad;
				else if (padflg && (datacnt == 15))
					begin
						nextstate = senddata;
						fulllength = 1;
					end
				else
					nextstate = idle;
			end
		datapad:
		 	begin
		 		datainc = 0;
		 		if ((datalength[8:6] == 7) || (datalength[8:0] == 0))
		 			begin
		 				expadflg = 1;
		 				nextstate = senddata;
		 			end
		 		else
		 			nextstate = lengthpad;
		 	end
		lengthpad:
			begin
				nextstate = senddata;
			end
		senddata:
			begin
				datainc = 0;
				datacntclr = 1;
				paddataready = 1;
				nextstate = idle;
			end
		expad:
			begin
				paddataready = 1;
				expadflgclr = 1;
				nextstate = idle;
			end
		sendmd1:
			begin
				md1ready =1;
				nextstate = waitmd2;
			end
		waitmd2: