bit4_2comp.v

来自「hmac的verilog代码, 通过控制字选择进行sha1运算或hmac运算」· Verilog 代码 · 共 34 行

//////////////////////////////////////////////////////////
//    module describe
// name: 		4-2 compressor(1 bit)
// function:	reduce the delay time for the add function
// writer:		zy
// data:		2006/04/01
// version:		1.0
// feature:		
//////////////////////////////////////////////////////////
 
 module bit4_2comp(a,b,c,d,x1_in,sum,x1_out,carry);
 
 input a;
 input b;
 input c;
 input d;
 input x1_in;
 
 output sum;
 output x1_out;
 output carry;
 
 reg sum;
 reg x1_out;
 reg carry;
 
 always @(a or b or c or d or x1_in)
 begin
 	x1_out<=((a^b)&c)|(a&b);
 	sum<=a^b^c^d^x1_in;
 	carry<=((a^b^c^d)&x1_in)|((a^b^c)&d);
 end

endmodule