shacoreunit_cmp_ap.v

hmac的verilog代码, 通过控制字选择进行sha1运算或hmac运算

///////////////////////////////////////////////////////
//    module describe
// name: 		shacoreunit
// function:	sha compress
// writer:		zy
// data:		2006/03/02
// version:		1.0
// feature:		
////////////////////////////////////////////////////////

module shacaoreunit(clk,reset,dataready,wt,procsel,newhmac,ivrst,modsel,hashready,digestout);

input clk;
input reset;
input dataready;
input [31:0] wt;
input [1:0] procsel;
input newhmac;
input ivrst;
input modsel;

output hashready;
output [159:0] digestout;

wire [31:0] va_add1;
wire [31:0] va_add2;
wire [31:0] sum_va;

wire [31:0] digest1;
wire [31:0] digest2;
wire [31:0] digest3;
wire [31:0] digest4;
wire [31:0] digest5;

reg [31:0] iva;
reg [31:0] ivatmp;
reg [31:0] ivb;
reg [31:0] ivbtmp;
reg [31:0] ivc;
reg [31:0] ivctmp;
reg [31:0] ivd;
reg [31:0] ivdtmp;
reg [31:0] ive;
reg [31:0] ivetmp;
reg [31:0] rva;
reg [31:0] rvb;
reg [31:0] rvc;
reg [31:0] rvd;
reg [31:0] rve;
reg [31:0] rv1a;
reg [31:0] rv1b;
reg [31:0] rv1c;
reg [31:0] rv1d;
reg [31:0] rv1e;
reg [31:0] rv2a;
reg [31:0] rv2b;
reg [31:0] rv2c;
reg [31:0] rv2d;
reg [31:0] rv2e;
reg [31:0] f;
reg [31:0] s5a;
reg [4:0] intercnt;
reg [4:0] intercnttmp;
reg [1:0] roundcnt;
reg [1:0] roundcnttmp;
reg hashready;
reg hashreadytmp;
reg [159:0]digestout;
reg cmpon;
reg cmpontmp;
reg lastround;
reg lastroundtmp;
reg [31:0] ve;


parameter a=32'h67452301;
parameter b=32'hefcdab89;
parameter c=32'h98badcfe;
parameter d=32'h10325476;
parameter e=32'hc3d2e1f0;

bit32_4_2comp bit32_4_2comp_v(ve,f,s5a,wt,va_add1,va_add2);

claa_32b claa_32_r(va_add1,va_add2,sum_va);

claa_32b claa_32_d1(iva,rva,digest1);
claa_32b claa_32_d2(ivb,rvb,digest2);
claa_32b claa_32_d3(ivc,rvc,digest3);
claa_32b claa_32_d4(ivd,rvd,digest4);
claa_32b claa_32_d5(ive,rve,digest5);

always @(intercnt or roundcnt or rve or ive)
begin
	if((roundcnt==0)&&(intercnt==0))
		ve<=rve;
	else 
		ve<=ive;
end

always @(posedge clk)
begin
	if (reset)
		begin
			iva<=a;
			ivb<=b;
			ivc<=c;
			ivd<=d;
			ive<=e;
			intercnt<=0;
			roundcnt<=0;
			hashready<=0;
			lastround<=0;
			cmpon<=0;
			end
	else 
		begin
			iva<=ivatmp;
			ivb<=ivbtmp;
			ivc<=ivctmp;
			ivd<=ivdtmp;
			ive<=ivetmp;
			intercnt<=intercnttmp;
			roundcnt<=roundcnttmp;
			hashready<=hashreadytmp;
			lastround<=lastroundtmp;
			cmpon<=cmpontmp;
		end
end

always @(dataready or hashready or cmpon)
begin
	if (dataready)
		begin
			cmpontmp<=1;
		end
	else if (hashready)
		begin
			cmpontmp<=0;
		end
	else
		begin
			cmpontmp<=cmpon;
		end
end

always @(intercnt or roundcnt or cmpon or hashready or rva or rvb or rvc or rvd or rve or iva or ivb or ivc or ivd or ive or sum_va)
begin
	if (cmpon)
		begin
			case (roundcnt)
				0:
				begin
					if (intercnt==0)
						begin
							ivatmp<=sum_va;
							ivbtmp<=rva;
							ivctmp<={rvb[1:0],rvb[31:2]};
							ivdtmp<=rvc;
							ivetmp<=rvd;
						end
					
					else
						begin	
							ivatmp<=sum_va;
							ivbtmp<=iva;
							ivctmp<={ivb[1:0],ivb[31:2]};
							ivdtmp<=ivc;
							ivetmp<=ivd;
						end
				end
				1:
				begin
					ivatmp<=sum_va;
					ivbtmp<=iva;
					ivctmp<={ivb[1:0],ivb[31:2]};
					ivdtmp<=ivc;
					ivetmp<=ivd;
				end
				2:
				begin
					ivatmp<=sum_va;
					ivbtmp<=iva;
					ivctmp<={ivb[1:0],ivb[31:2]};
					ivdtmp<=ivc;
					ivetmp<=ivd;
				end
				3:
				begin
					ivatmp<=sum_va;
					ivbtmp<=iva;
					ivctmp<={ivb[1:0],ivb[31:2]};
					ivdtmp<=ivc;
					ivetmp<=ivd;
				end
			endcase
		end
 	else if(hashready)
		begin
			ivatmp<=rva;
			ivbtmp<=rvb;
			ivctmp<=rvc;
			ivdtmp<=rvd;
			ivetmp<=rve;
		end
	else 
		begin
			ivatmp<=iva;
			ivbtmp<=ivb;
			ivctmp<=ivc;
			ivdtmp<=ivd;
			ivetmp<=ive;
		end
 
end

always @(intercnt or roundcnt or wt or cmpon or lastround or dataready)
begin
	if ((!cmpon)&&(dataready))
		begin	
			intercnttmp<=0;
			roundcnttmp<=0;
			lastroundtmp<=0;
		end
		
	else if ((cmpon)&&(!lastround))
		begin
			if (intercnt==19)
		  		begin
		  			intercnttmp<=0;
		  			if (roundcnt==3)
		  				begin
		  					roundcnttmp<=0;
		  					lastroundtmp<=1;
		  				end
		  			else 
		  				begin
		  					roundcnttmp<=roundcnt+1;
		  					lastroundtmp<=0;
		  				end
		  		end
		  	else 
		  		begin 
					intercnttmp <=intercnt +1;
					roundcnttmp <=roundcnt;
					lastroundtmp <=0;
				end
		end
	else
		begin
			intercnttmp<=intercnt;
			roundcnttmp<=roundcnt;
			lastroundtmp<=0;
		end
end

always @(intercnt or roundcnt or hashready or ivb or ivc or ivd or rvc or rvd or rvb)
begin
	case (roundcnt)
	0: 	
		begin
			if ((!roundcnt)&&(!intercnt))
				f<=(rvb&rvc)|((~rvb)&rvd);
			else
				f<=(ivb&ivc)|((~ivb)&ivd);
		end
	1:	f<=ivb^ivc^ivd;
	2:	f<=(ivb&ivc)|(ivb&ivd)|(ivc&ivd);
	3:	f<=ivb^ivc^ivd;
	endcase
end

always @(intercnt or roundcnt or hashready or iva or rva)
begin
	if ((!intercnt)&&(!roundcnt))
		s5a<={rva[26:0],rva[31:27]};
	else
		s5a<={iva[26:0],iva[31:27]};
end
	
always @(posedge clk)
begin
	if (reset)
		begin
			digestout<=0;
			hashreadytmp<=0;
			rv1a <= 0;
			rv1b <= 0;
			rv1c <= 0;
			rv1d <= 0;
			rv1e <= 0;
			rv2a <= 0;
			rv2b <= 0;
			rv2c <= 0;
			rv2d <= 0;
			rv2e <= 0;
		end
		  
	else if (lastround)
		begin
			case (procsel)
				0,3:
					begin
						digestout[159:128]	<= digest1;
						digestout[127:96]	  <= digest2;
						digestout[95:64]	  <= digest3;
						digestout[63:32]	  <= digest4;
						digestout[31:0]		  <= digest5;
					end
				1:
					begin
						rv1a <= digest1;
						rv1b <= digest2;
						rv1c <= digest3;
						rv1d <= digest4;
						rv1e <= digest5;
					end	
				2:
					begin
						rv2a <= digest1;
						rv2b <= digest2;
						rv2c <= digest3;
						rv2d <= digest4;
						rv2e <= digest5;
					end	
			endcase
			hashreadytmp<=1;
		end
		
	else
		begin
			hashreadytmp<=0;
		end

end

always @(posedge clk)
begin
	if (reset || ivrst)
		begin
			rva<=a;
			rvb<=b;
			rvc<=c;
			rvd<=d;
			rve<=e;		
		end
	else
		case (procsel)
		0:
			begin
				if (newhmac && modsel && dataready)
					begin
						rva<=rv1a;
						rvb<=rv1b;
						rvc<=rv1c;
						rvd<=rv1d;
						rve<=rv1e;
					end
				else if (hashready)
					begin
						rva<=digestout[159:128];
						rvb<=digestout[127:96];
						rvc<=digestout[95:64];
						rvd<=digestout[63:32];
						rve<=digestout[31:0];
					end
			end
		1:
			begin
				rva<=a;
				rvb<=b;
				rvc<=c;
				rvd<=d;
				rve<=e;		
			end
		2:
			begin
				rva<=a;
				rvb<=b;
				rvc<=c;
				rvd<=d;
				rve<=e;
			end
		3:
			begin
				rva<=rv2a;
				rvb<=rv2b;
				rvc<=rv2c;
				rvd<=rv2d;
				rve<=rv2e;
			end
	endcase
end

endmodule