yimaqi.laf

3-8译码器学校课程设计上载以大家共享

LAF 01.03.00 L;
SECTION HEADER ;
 DESIGN yimaqi 0.0 ;
 STAT edif2laf 1.0 10.4.2006 20.22.20 1 ;
END ;
SECTION DEVICE ;
 TECHNOLOGY pLSI;
 PART ispLSI1032E-100LJ84;
END ;
SECTION LOGICAL ;
  XPIN Y7 OUT OUT_Y7_U1_XO0 ;
  XPIN Y6 OUT OUT_Y6_U1_XO0 ;
  XPIN Y5 OUT OUT_Y5_U1_XO0 ;
  XPIN Y4 OUT OUT_Y4_U1_XO0 ;
  XPIN Y3 OUT OUT_Y3_U1_XO0 ;
  XPIN Y2 OUT OUT_Y2_U1_XO0 ;
  XPIN Y1 OUT OUT_Y1_U1_XO0 ;
  XPIN Y0 OUT OUT_Y0_U1_XO0 ;
  XPIN C IN C ;
  XPIN B IN B ;
  XPIN A IN A ;
  NET C  EXT  DST IN_C_U1_$1I45.XI0 ;
  NET B  EXT  DST IN_B_U1_$1I45.XI0 ;
  NET A  EXT  DST IN_A_U1_$1I45.XI0 ;
  NET I12_ZN0  SRC I12.ZN0  DST OUT_Y0_U1_$1I42.A0 ;
  NET I10_ZN0  SRC I10.ZN0  DST OUT_Y1_U1_$1I42.A0 ;
  NET I9_ZN0  SRC I9.ZN0  DST OUT_Y2_U1_$1I42.A0 ;
  NET I8_ZN0  SRC I8.ZN0  DST OUT_Y3_U1_$1I42.A0 ;
  NET I7_ZN0  SRC I7.ZN0  DST OUT_Y4_U1_$1I42.A0 ;
  NET I6_ZN0  SRC I6.ZN0  DST OUT_Y6_U1_$1I42.A0 ;
  NET I5_ZN0  SRC I5.ZN0  DST OUT_Y7_U1_$1I42.A0 ;
  NET I4_ZN0  SRC I4.ZN0  DST OUT_Y5_U1_$1I42.A0 ;
  NET I3_ZN0  SRC I3.ZN0  DST I10.A2 I4.A2 I5.A2 I8.A2 ;
  NET I2_ZN0  SRC I2.ZN0  DST I5.A1 I6.A1 I8.A1 I9.A1 ;
  NET I1_ZN0  SRC I1.ZN0  DST I4.A0 I5.A0 I6.A0 I7.A0 ;
  NET OUT_Y7_U1_XO0 EXT  SRC OUT_Y7_U1_$1I42.XO0 ;
  NET OUT_Y6_U1_XO0 EXT  SRC OUT_Y6_U1_$1I42.XO0 ;
  NET OUT_Y5_U1_XO0 EXT  SRC OUT_Y5_U1_$1I42.XO0 ;
  NET OUT_Y4_U1_XO0 EXT  SRC OUT_Y4_U1_$1I42.XO0 ;
  NET OUT_Y3_U1_XO0 EXT  SRC OUT_Y3_U1_$1I42.XO0 ;
  NET OUT_Y2_U1_XO0 EXT  SRC OUT_Y2_U1_$1I42.XO0 ;
  NET OUT_Y1_U1_XO0 EXT  SRC OUT_Y1_U1_$1I42.XO0 ;
  NET OUT_Y0_U1_XO0 EXT  SRC OUT_Y0_U1_$1I42.XO0 ;
  NET IN_C_U1_Z0  SRC IN_C_U1_$1I45.Z0  DST I3.A0 I12.A2 I6.A2 I7.A2 I9.A2 ;
  NET IN_B_U1_Z0  SRC IN_B_U1_$1I45.Z0  DST I2.A0 I10.A1 I12.A1 I4.A1 I7.A1 ;
  NET IN_A_U1_Z0  SRC IN_A_U1_$1I45.Z0  DST I1.A0 I10.A0 I12.A0 I8.A0 I9.A0 ;
 SYM INV I1;
   PIN ZN0 OUT I1_ZN0;
   PIN A0 IN IN_A_U1_Z0;
 END;
 SYM INV I2;
   PIN ZN0 OUT I2_ZN0;
   PIN A0 IN IN_B_U1_Z0;
 END;
 SYM INV I3;
   PIN ZN0 OUT I3_ZN0;
   PIN A0 IN IN_C_U1_Z0;
 END;
 SYM NAND3 I10;
   PIN ZN0 OUT I10_ZN0;
   PIN A0 IN IN_A_U1_Z0;
   PIN A1 IN IN_B_U1_Z0;
   PIN A2 IN I3_ZN0;
 END;
 SYM NAND3 I12;
   PIN ZN0 OUT I12_ZN0;
   PIN A0 IN IN_A_U1_Z0;
   PIN A1 IN IN_B_U1_Z0;
   PIN A2 IN IN_C_U1_Z0;
 END;
 SYM NAND3 I4;
   PIN ZN0 OUT I4_ZN0;
   PIN A0 IN I1_ZN0;
   PIN A1 IN IN_B_U1_Z0;
   PIN A2 IN I3_ZN0;
 END;
 SYM NAND3 I5;
   PIN ZN0 OUT I5_ZN0;
   PIN A0 IN I1_ZN0;
   PIN A1 IN I2_ZN0;
   PIN A2 IN I3_ZN0;
 END;
 SYM NAND3 I6;
   PIN ZN0 OUT I6_ZN0;
   PIN A0 IN I1_ZN0;
   PIN A1 IN I2_ZN0;
   PIN A2 IN IN_C_U1_Z0;
 END;
 SYM NAND3 I7;
   PIN ZN0 OUT I7_ZN0;
   PIN A0 IN I1_ZN0;
   PIN A1 IN IN_B_U1_Z0;
   PIN A2 IN IN_C_U1_Z0;
 END;
 SYM NAND3 I8;
   PIN ZN0 OUT I8_ZN0;
   PIN A0 IN IN_A_U1_Z0;
   PIN A1 IN I2_ZN0;
   PIN A2 IN I3_ZN0;
 END;
 SYM NAND3 I9;
   PIN ZN0 OUT I9_ZN0;
   PIN A0 IN IN_A_U1_Z0;
   PIN A1 IN I2_ZN0;
   PIN A2 IN IN_C_U1_Z0;
 END;
 SYM XOUTPUT OUT_Y7_U1_$1I42;
   PIN XO0 OUT OUT_Y7_U1_XO0;
   PIN A0 IN I5_ZN0;
 END;
 SYM XOUTPUT OUT_Y6_U1_$1I42;
   PIN XO0 OUT OUT_Y6_U1_XO0;
   PIN A0 IN I6_ZN0;
 END;
 SYM XOUTPUT OUT_Y5_U1_$1I42;
   PIN XO0 OUT OUT_Y5_U1_XO0;
   PIN A0 IN I4_ZN0;
 END;
 SYM XOUTPUT OUT_Y4_U1_$1I42;
   PIN XO0 OUT OUT_Y4_U1_XO0;
   PIN A0 IN I7_ZN0;
 END;
 SYM XOUTPUT OUT_Y3_U1_$1I42;
   PIN XO0 OUT OUT_Y3_U1_XO0;
   PIN A0 IN I8_ZN0;
 END;
 SYM XOUTPUT OUT_Y2_U1_$1I42;
   PIN XO0 OUT OUT_Y2_U1_XO0;
   PIN A0 IN I9_ZN0;
 END;
 SYM XOUTPUT OUT_Y1_U1_$1I42;
   PIN XO0 OUT OUT_Y1_U1_XO0;
   PIN A0 IN I10_ZN0;
 END;
 SYM XOUTPUT OUT_Y0_U1_$1I42;
   PIN XO0 OUT OUT_Y0_U1_XO0;
   PIN A0 IN I12_ZN0;
 END;
 SYM XINPUT IN_C_U1_$1I45;
   PIN Z0 OUT IN_C_U1_Z0;
   PIN XI0 IN C;
 END;
 SYM XINPUT IN_B_U1_$1I45;
   PIN Z0 OUT IN_B_U1_Z0;
   PIN XI0 IN B;
 END;
 SYM XINPUT IN_A_U1_$1I45;
   PIN Z0 OUT IN_A_U1_Z0;
   PIN XI0 IN A;
 END;
END ;
END ;