yimaqi.sim

3-8译码器学校课程设计上载以大家共享

   SYM PGXOR2 GLB_D6_X2O GLB glb00;
      PIN  Z0  OUT  D6_X2O;
      PIN  A1  IN  D6_P4_xa;
      PIN  A0  IN  D6_G1;
   END;  // SYM PGXOR2

   SYM PGXOR2 GLB_D6_X1O GLB glb00;
      PIN  Z0  OUT  D6_X1O;
      PIN  A1  IN  D6_P8_xa;
      PIN  A0  IN  D6_G2;
   END;  // SYM PGXOR2

   SYM PGXOR2 GLB_D6_X0O GLB glb00;
      PIN  Z0  OUT  D6_X0O;
      PIN  A1  IN  D6_P13_xa;
      PIN  A0  IN  D6_G3;
   END;  // SYM PGXOR2

   SYM PGINVI GLB_D6_IN15B GLB glb00;
      PIN  ZN0  OUT  D6_IN15B;
      PIN  A0  IN  AX_grp;
   END;  // SYM PGINVI

   SYM PGINVI GLB_D6_IN4B GLB glb00;
      PIN  ZN0  OUT  D6_IN4B;
      PIN  A0  IN  BX_grp;
   END;  // SYM PGINVI

   SYM PGINVI GLB_D6_IN14B GLB glb00;
      PIN  ZN0  OUT  D6_IN14B;
      PIN  A0  IN  CX_grp;
   END;  // SYM PGINVI

   SYM PXIN IOC_IO1_IBUFO IOC C;
      PIN  Z0  OUT  IO1_IBUFO;
      PIN  XI0  IN  C;
   END;  // SYM PXIN

   SYM PXIN IOC_IO43_IBUFO IOC B;
      PIN  Z0  OUT  IO43_IBUFO;
      PIN  XI0  IN  B;
   END;  // SYM PXIN

   SYM PXIN IOC_IO11_IBUFO IOC A;
      PIN  Z0  OUT  IO11_IBUFO;
      PIN  XI0  IN  A;
   END;  // SYM PXIN

   SYM PXOUT IOC_Y7 IOC Y7;
      PIN  XO0  OUT  Y7;
      PIN  A0  IN  IO48_OBUFI;
   END;  // SYM PXOUT

   SYM PGINVI IOC_IO48_OBUFI IOC Y7;
      PIN  ZN0  OUT  IO48_OBUFI;
      PIN  A0  IN  AND_735_iomux;
   END;  // SYM PXINVO

   SYM PXOUT IOC_Y6 IOC Y6;
      PIN  XO0  OUT  Y6;
      PIN  A0  IN  IO0_OBUFI;
   END;  // SYM PXOUT

   SYM PGINVI IOC_IO0_OBUFI IOC Y6;
      PIN  ZN0  OUT  IO0_OBUFI;
      PIN  A0  IN  AND_734_iomux;
   END;  // SYM PXINVO

   SYM PXOUT IOC_Y5 IOC Y5;
      PIN  XO0  OUT  Y5;
      PIN  A0  IN  IO5_OBUFI;
   END;  // SYM PXOUT

   SYM PGINVI IOC_IO5_OBUFI IOC Y5;
      PIN  ZN0  OUT  IO5_OBUFI;
      PIN  A0  IN  AND_733_iomux;
   END;  // SYM PXINVO

   SYM PXOUT IOC_Y4 IOC Y4;
      PIN  XO0  OUT  Y4;
      PIN  A0  IN  IO2_OBUFI;
   END;  // SYM PXOUT

   SYM PGINVI IOC_IO2_OBUFI IOC Y4;
      PIN  ZN0  OUT  IO2_OBUFI;
      PIN  A0  IN  AND_732_iomux;
   END;  // SYM PXINVO

   SYM PXOUT IOC_Y3 IOC Y3;
      PIN  XO0  OUT  Y3;
      PIN  A0  IN  IO3_OBUFI;
   END;  // SYM PXOUT

   SYM PGINVI IOC_IO3_OBUFI IOC Y3;
      PIN  ZN0  OUT  IO3_OBUFI;
      PIN  A0  IN  AND_731_iomux;
   END;  // SYM PXINVO

   SYM PXOUT IOC_Y2 IOC Y2;
      PIN  XO0  OUT  Y2;
      PIN  A0  IN  IO49_OBUFI;
   END;  // SYM PXOUT

   SYM PGINVI IOC_IO49_OBUFI IOC Y2;
      PIN  ZN0  OUT  IO49_OBUFI;
      PIN  A0  IN  AND_730_iomux;
   END;  // SYM PXINVO

   SYM PXOUT IOC_Y1 IOC Y1;
      PIN  XO0  OUT  Y1;
      PIN  A0  IN  IO50_OBUFI;
   END;  // SYM PXOUT

   SYM PGINVI IOC_IO50_OBUFI IOC Y1;
      PIN  ZN0  OUT  IO50_OBUFI;
      PIN  A0  IN  AND_729_iomux;
   END;  // SYM PXINVO

   SYM PXOUT IOC_Y0 IOC Y0;
      PIN  XO0  OUT  Y0;
      PIN  A0  IN  IO51_OBUFI;
   END;  // SYM PXOUT

   SYM PGINVI IOC_IO51_OBUFI IOC Y0;
      PIN  ZN0  OUT  IO51_OBUFI;
      PIN  A0  IN  AND_728_iomux;
   END;  // SYM PXINVO

   SYM PGBUFI GRP_AND_734_iomux  GRP;
      PIN  Z0  OUT  AND_734_iomux;
      PIN  A0  IN  AND_734;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_AND_733_iomux  GRP;
      PIN  Z0  OUT  AND_733_iomux;
      PIN  A0  IN  AND_733;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_AND_732_iomux  GRP;
      PIN  Z0  OUT  AND_732_iomux;
      PIN  A0  IN  AND_732;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_AND_731_iomux  GRP;
      PIN  Z0  OUT  AND_731_iomux;
      PIN  A0  IN  AND_731;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_AX_grp  GRP;
      PIN  Z0  OUT  AX_grp;
      PIN  A0  IN  IO11_IBUFO;
   END;  // SYM PRBUFO2

   SYM PGBUFI GRP_BX_grp  GRP;
      PIN  Z0  OUT  BX_grp;
      PIN  A0  IN  IO43_IBUFO;
   END;  // SYM PRBUFO2

   SYM PGBUFI GRP_CX_grp  GRP;
      PIN  Z0  OUT  CX_grp;
      PIN  A0  IN  IO1_IBUFO;
   END;  // SYM PRBUFO2

   SYM PGBUFI GRP_AND_735_iomux  GRP;
      PIN  Z0  OUT  AND_735_iomux;
      PIN  A0  IN  AND_735;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_AND_730_iomux  GRP;
      PIN  Z0  OUT  AND_730_iomux;
      PIN  A0  IN  AND_730;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_AND_729_iomux  GRP;
      PIN  Z0  OUT  AND_729_iomux;
      PIN  A0  IN  AND_729;
   END;  // SYM PRBUFX1

   SYM PGBUFI GRP_AND_728_iomux  GRP;
      PIN  Z0  OUT  AND_728_iomux;
      PIN  A0  IN  AND_728;
   END;  // SYM PRBUFX1
END;  // PHYSSIM SECTION

SECTION INSTANCE_TIMING_DATA;

// File created on Mon Apr 10 20:22:02 2006


// Copyright (c) Lattice Semiconductor Corp. 1992. All rights reserved.

// Part used: ispLSI1032E-100LJ84

// Device speed in units of hundredpsec
GLB_A6_P13 HL 25:0:25
GLB_A6_P13 LH 25:0:25
GLB_A6_P8 HL 25:0:25
GLB_A6_P8 LH 25:0:25
GLB_A6_P4 HL 25:0:25
GLB_A6_P4 LH 25:0:25
GLB_A6_P0 HL 25:0:25
GLB_A6_P0 LH 25:0:25
GLB_A6_G3 HL 7:0:7
GLB_A6_G3 LH 7:0:7
GLB_A6_G2 HL 7:0:7
GLB_A6_G2 LH 7:0:7
GLB_A6_G1 HL 7:0:7
GLB_A6_G1 LH 7:0:7
GLB_A6_G0 HL 7:0:7
GLB_A6_G0 LH 7:0:7
GLB_A6_P0_xa HL 8:0:8
GLB_A6_P0_xa LH 8:0:8
GLB_AND_731 HL 10:0:10
GLB_AND_731 LH 10:0:10
GLB_A6_P4_xa HL 8:0:8
GLB_A6_P4_xa LH 8:0:8
GLB_AND_732 HL 10:0:10
GLB_AND_732 LH 10:0:10
GLB_A6_P8_xa HL 8:0:8
GLB_A6_P8_xa LH 8:0:8
GLB_AND_733 HL 10:0:10
GLB_AND_733 LH 10:0:10
GLB_A6_P13_xa HL 8:0:8
GLB_A6_P13_xa LH 8:0:8
GLB_AND_734 HL 10:0:10
GLB_AND_734 LH 10:0:10
GLB_A6_IN11 HL 10:0:10
GLB_A6_IN11 LH 10:0:10
GLB_A6_IN1 HL 10:0:10
GLB_A6_IN1 LH 10:0:10
GLB_A6_IN0 HL 10:0:10
GLB_A6_IN0 LH 10:0:10
GLB_A6_X3O HL 3:0:3
GLB_A6_X3O LH 3:0:3
GLB_A6_X2O HL 3:0:3
GLB_A6_X2O LH 3:0:3
GLB_A6_X1O HL 3:0:3
GLB_A6_X1O LH 3:0:3
GLB_A6_X0O HL 3:0:3
GLB_A6_X0O LH 3:0:3
GLB_A6_IN0B HL 10:0:10
GLB_A6_IN0B LH 10:0:10
GLB_A6_IN11B HL 10:0:10
GLB_A6_IN11B LH 10:0:10
GLB_A6_IN1B HL 10:0:10
GLB_A6_IN1B LH 10:0:10
GLB_D6_P13 HL 25:0:25
GLB_D6_P13 LH 25:0:25
GLB_D6_P8 HL 25:0:25
GLB_D6_P8 LH 25:0:25
GLB_D6_P4 HL 25:0:25
GLB_D6_P4 LH 25:0:25
GLB_D6_P0 HL 25:0:25
GLB_D6_P0 LH 25:0:25
GLB_D6_G3 HL 7:0:7
GLB_D6_G3 LH 7:0:7
GLB_D6_G2 HL 7:0:7
GLB_D6_G2 LH 7:0:7
GLB_D6_G1 HL 7:0:7
GLB_D6_G1 LH 7:0:7
GLB_D6_G0 HL 7:0:7
GLB_D6_G0 LH 7:0:7
GLB_D6_P0_xa HL 8:0:8
GLB_D6_P0_xa LH 8:0:8
GLB_AND_728 HL 10:0:10
GLB_AND_728 LH 10:0:10
GLB_D6_P4_xa HL 8:0:8
GLB_D6_P4_xa LH 8:0:8
GLB_AND_729 HL 10:0:10
GLB_AND_729 LH 10:0:10
GLB_D6_P8_xa HL 8:0:8
GLB_D6_P8_xa LH 8:0:8
GLB_AND_730 HL 10:0:10
GLB_AND_730 LH 10:0:10
GLB_D6_P13_xa HL 8:0:8
GLB_D6_P13_xa LH 8:0:8
GLB_AND_735 HL 10:0:10
GLB_AND_735 LH 10:0:10
GLB_D6_IN15 HL 10:0:10
GLB_D6_IN15 LH 10:0:10
GLB_D6_IN14 HL 10:0:10
GLB_D6_IN14 LH 10:0:10
GLB_D6_IN4 HL 10:0:10
GLB_D6_IN4 LH 10:0:10
GLB_D6_X3O HL 3:0:3
GLB_D6_X3O LH 3:0:3
GLB_D6_X2O HL 3:0:3
GLB_D6_X2O LH 3:0:3
GLB_D6_X1O HL 3:0:3
GLB_D6_X1O LH 3:0:3
GLB_D6_X0O HL 3:0:3
GLB_D6_X0O LH 3:0:3
GLB_D6_IN15B HL 10:0:10
GLB_D6_IN15B LH 10:0:10
GLB_D6_IN4B HL 10:0:10
GLB_D6_IN4B LH 10:0:10
GLB_D6_IN14B HL 10:0:10
GLB_D6_IN14B LH 10:0:10
IOC_IO1_IBUFO HL 3:0:3
IOC_IO1_IBUFO LH 3:0:3
IOC_IO43_IBUFO HL 3:0:3
IOC_IO43_IBUFO LH 3:0:3
IOC_IO11_IBUFO HL 3:0:3
IOC_IO11_IBUFO LH 3:0:3
IOC_Y7 HL 16:0:16
IOC_Y7 LH 16:0:16
IOC_IO48_OBUFI HL 4:0:4
IOC_IO48_OBUFI LH 4:0:4
IOC_Y6 HL 16:0:16
IOC_Y6 LH 16:0:16
IOC_IO0_OBUFI HL 4:0:4
IOC_IO0_OBUFI LH 4:0:4
IOC_Y5 HL 16:0:16
IOC_Y5 LH 16:0:16
IOC_IO5_OBUFI HL 4:0:4
IOC_IO5_OBUFI LH 4:0:4
IOC_Y4 HL 16:0:16
IOC_Y4 LH 16:0:16
IOC_IO2_OBUFI HL 4:0:4
IOC_IO2_OBUFI LH 4:0:4
IOC_Y3 HL 16:0:16
IOC_Y3 LH 16:0:16
IOC_IO3_OBUFI HL 4:0:4
IOC_IO3_OBUFI LH 4:0:4
IOC_Y2 HL 16:0:16
IOC_Y2 LH 16:0:16
IOC_IO49_OBUFI HL 4:0:4
IOC_IO49_OBUFI LH 4:0:4
IOC_Y1 HL 16:0:16
IOC_Y1 LH 16:0:16
IOC_IO50_OBUFI HL 4:0:4
IOC_IO50_OBUFI LH 4:0:4
IOC_Y0 HL 16:0:16
IOC_Y0 LH 16:0:16
IOC_IO51_OBUFI HL 4:0:4
IOC_IO51_OBUFI LH 4:0:4
GRP_AND_734_iomux HL 10:0:10
GRP_AND_734_iomux LH 10:0:10
GRP_AND_733_iomux HL 10:0:10
GRP_AND_733_iomux LH 10:0:10
GRP_AND_732_iomux HL 10:0:10
GRP_AND_732_iomux LH 10:0:10
GRP_AND_731_iomux HL 10:0:10
GRP_AND_731_iomux LH 10:0:10
GRP_AX_grp HL 20:0:20
GRP_AX_grp LH 20:0:20
GRP_BX_grp HL 20:0:20
GRP_BX_grp LH 20:0:20
GRP_CX_grp HL 20:0:20
GRP_CX_grp LH 20:0:20
GRP_AND_735_iomux HL 10:0:10
GRP_AND_735_iomux LH 10:0:10
GRP_AND_730_iomux HL 10:0:10
GRP_AND_730_iomux LH 10:0:10
GRP_AND_729_iomux HL 10:0:10
GRP_AND_729_iomux LH 10:0:10
GRP_AND_728_iomux HL 10:0:10
GRP_AND_728_iomux LH 10:0:10

END; // TIMING

END;  // LAF