📄 yimaqi.sim
字号:
LAF 1.4.1 S;
SECTION HEADER;
DESIGN yimaqi 0.0;
END; // HEADER SECTION
SECTION DEVICE;
TECHNOLOGY ispLSI;
PART ispLSI1032E-100LJ84;
END; // DEVICE SECTION
SECTION PHYSSIM;
XPIN C IN C XTYPE IO LOCK 27;
XPIN B IN B XTYPE IO LOCK 79;
XPIN A IN A XTYPE IO LOCK 37;
XPIN Y7 OUT Y7 XTYPE IO LOCK 3;
XPIN Y6 OUT Y6 XTYPE IO LOCK 26;
XPIN Y5 OUT Y5 XTYPE IO LOCK 31;
XPIN Y4 OUT Y4 XTYPE IO LOCK 28;
XPIN Y3 OUT Y3 XTYPE IO LOCK 29;
XPIN Y2 OUT Y2 XTYPE IO LOCK 4;
XPIN Y1 OUT Y1 XTYPE IO LOCK 5;
XPIN Y0 OUT Y0 XTYPE IO LOCK 6;
NET C EXT DST IOC_IO1_IBUFO.XI0;
NET IO1_IBUFO SRC IOC_IO1_IBUFO.Z0 DST GRP_CX_grp.A0;
NET B EXT DST IOC_IO43_IBUFO.XI0;
NET IO43_IBUFO SRC IOC_IO43_IBUFO.Z0 DST GRP_BX_grp.A0;
NET A EXT DST IOC_IO11_IBUFO.XI0;
NET IO11_IBUFO SRC IOC_IO11_IBUFO.Z0 DST GRP_AX_grp.A0;
NET Y7 EXT SRC IOC_Y7.XO0;
NET IO48_OBUFI SRC IOC_IO48_OBUFI.ZN0 DST IOC_Y7.A0;
NET AND_735_iomux SRC GRP_AND_735_iomux.Z0 DST IOC_IO48_OBUFI.A0;
NET Y6 EXT SRC IOC_Y6.XO0;
NET IO0_OBUFI SRC IOC_IO0_OBUFI.ZN0 DST IOC_Y6.A0;
NET AND_734_iomux SRC GRP_AND_734_iomux.Z0 DST IOC_IO0_OBUFI.A0;
NET Y5 EXT SRC IOC_Y5.XO0;
NET IO5_OBUFI SRC IOC_IO5_OBUFI.ZN0 DST IOC_Y5.A0;
NET AND_733_iomux SRC GRP_AND_733_iomux.Z0 DST IOC_IO5_OBUFI.A0;
NET Y4 EXT SRC IOC_Y4.XO0;
NET IO2_OBUFI SRC IOC_IO2_OBUFI.ZN0 DST IOC_Y4.A0;
NET AND_732_iomux SRC GRP_AND_732_iomux.Z0 DST IOC_IO2_OBUFI.A0;
NET Y3 EXT SRC IOC_Y3.XO0;
NET IO3_OBUFI SRC IOC_IO3_OBUFI.ZN0 DST IOC_Y3.A0;
NET AND_731_iomux SRC GRP_AND_731_iomux.Z0 DST IOC_IO3_OBUFI.A0;
NET Y2 EXT SRC IOC_Y2.XO0;
NET IO49_OBUFI SRC IOC_IO49_OBUFI.ZN0 DST IOC_Y2.A0;
NET AND_730_iomux SRC GRP_AND_730_iomux.Z0 DST IOC_IO49_OBUFI.A0;
NET Y1 EXT SRC IOC_Y1.XO0;
NET IO50_OBUFI SRC IOC_IO50_OBUFI.ZN0 DST IOC_Y1.A0;
NET AND_729_iomux SRC GRP_AND_729_iomux.Z0 DST IOC_IO50_OBUFI.A0;
NET Y0 EXT SRC IOC_Y0.XO0;
NET IO51_OBUFI SRC IOC_IO51_OBUFI.ZN0 DST IOC_Y0.A0;
NET AND_728_iomux SRC GRP_AND_728_iomux.Z0 DST IOC_IO51_OBUFI.A0;
NET A6_P0_xa SRC GLB_A6_P0_xa.Z0 DST GLB_A6_X3O.A1;
NET AND_731 SRC GLB_AND_731.Z0 DST GRP_AND_731_iomux.A0;
NET A6_X3O SRC GLB_A6_X3O.Z0 DST GLB_AND_731.A0;
NET A6_P4_xa SRC GLB_A6_P4_xa.Z0 DST GLB_A6_X2O.A1;
NET AND_732 SRC GLB_AND_732.Z0 DST GRP_AND_732_iomux.A0;
NET A6_X2O SRC GLB_A6_X2O.Z0 DST GLB_AND_732.A0;
NET A6_P8_xa SRC GLB_A6_P8_xa.Z0 DST GLB_A6_X1O.A1;
NET AND_733 SRC GLB_AND_733.Z0 DST GRP_AND_733_iomux.A0;
NET A6_X1O SRC GLB_A6_X1O.Z0 DST GLB_AND_733.A0;
NET A6_P13_xa SRC GLB_A6_P13_xa.Z0 DST GLB_A6_X0O.A1;
NET AND_734 SRC GLB_AND_734.Z0 DST GRP_AND_734_iomux.A0;
NET A6_X0O SRC GLB_A6_X0O.Z0 DST GLB_AND_734.A0;
NET A6_G3 SRC GLB_A6_G3.Z0 DST GLB_A6_X0O.A0;
NET A6_G2 SRC GLB_A6_G2.Z0 DST GLB_A6_X1O.A0;
NET A6_G1 SRC GLB_A6_G1.Z0 DST GLB_A6_X2O.A0;
NET A6_G0 SRC GLB_A6_G0.Z0 DST GLB_A6_X3O.A0;
NET A6_P13 SRC GLB_A6_P13.Z0 DST GLB_A6_P13_xa.A0;
NET A6_P8 SRC GLB_A6_P8.Z0 DST GLB_A6_P8_xa.A0;
NET A6_P4 SRC GLB_A6_P4.Z0 DST GLB_A6_P4_xa.A0;
NET A6_IN0B SRC GLB_A6_IN0B.ZN0 DST GLB_A6_P13.A2 GLB_A6_P8.A2 GLB_A6_P4.A2;
NET A6_IN1 SRC GLB_A6_IN1.Z0 DST GLB_A6_P13.A1 GLB_A6_P4.A1;
NET A6_IN11 SRC GLB_A6_IN11.Z0 DST GLB_A6_P8.A0 GLB_A6_P4.A0;
NET A6_P0 SRC GLB_A6_P0.Z0 DST GLB_A6_P0_xa.A0;
NET A6_IN0 SRC GLB_A6_IN0.Z0 DST GLB_A6_P0.A2;
NET A6_IN1B SRC GLB_A6_IN1B.ZN0 DST GLB_A6_P8.A1 GLB_A6_P0.A1;
NET A6_IN11B SRC GLB_A6_IN11B.ZN0 DST GLB_A6_P13.A0 GLB_A6_P0.A0;
NET D6_P0_xa SRC GLB_D6_P0_xa.Z0 DST GLB_D6_X3O.A1;
NET AND_728 SRC GLB_AND_728.Z0 DST GRP_AND_728_iomux.A0;
NET D6_X3O SRC GLB_D6_X3O.Z0 DST GLB_AND_728.A0;
NET D6_P4_xa SRC GLB_D6_P4_xa.Z0 DST GLB_D6_X2O.A1;
NET AND_729 SRC GLB_AND_729.Z0 DST GRP_AND_729_iomux.A0;
NET D6_X2O SRC GLB_D6_X2O.Z0 DST GLB_AND_729.A0;
NET D6_P8_xa SRC GLB_D6_P8_xa.Z0 DST GLB_D6_X1O.A1;
NET AND_730 SRC GLB_AND_730.Z0 DST GRP_AND_730_iomux.A0;
NET D6_X1O SRC GLB_D6_X1O.Z0 DST GLB_AND_730.A0;
NET D6_P13_xa SRC GLB_D6_P13_xa.Z0 DST GLB_D6_X0O.A1;
NET AND_735 SRC GLB_AND_735.Z0 DST GRP_AND_735_iomux.A0;
NET D6_X0O SRC GLB_D6_X0O.Z0 DST GLB_AND_735.A0;
NET D6_G3 SRC GLB_D6_G3.Z0 DST GLB_D6_X0O.A0;
NET D6_G2 SRC GLB_D6_G2.Z0 DST GLB_D6_X1O.A0;
NET D6_G1 SRC GLB_D6_G1.Z0 DST GLB_D6_X2O.A0;
NET D6_G0 SRC GLB_D6_G0.Z0 DST GLB_D6_X3O.A0;
NET GND DST GLB_A6_G3.A0 GLB_A6_G2.A0 GLB_A6_G1.A0 GLB_A6_G0.A0 GLB_D6_G3.A0
GLB_D6_G2.A0 GLB_D6_G1.A0 GLB_D6_G0.A0;
NET D6_P13 SRC GLB_D6_P13.Z0 DST GLB_D6_P13_xa.A0;
NET D6_IN15B SRC GLB_D6_IN15B.ZN0 DST GLB_D6_P13.A0;
NET D6_P8 SRC GLB_D6_P8.Z0 DST GLB_D6_P8_xa.A0;
NET D6_IN4B SRC GLB_D6_IN4B.ZN0 DST GLB_D6_P13.A2 GLB_D6_P8.A2;
NET D6_P4 SRC GLB_D6_P4.Z0 DST GLB_D6_P4_xa.A0;
NET D6_IN14B SRC GLB_D6_IN14B.ZN0 DST GLB_D6_P13.A1 GLB_D6_P4.A1;
NET AX_grp SRC GRP_AX_grp.Z0 DST GLB_A6_IN0B.A0 GLB_A6_IN0.A0 GLB_D6_IN15B.A0 GLB_D6_IN15.A0;
NET CX_grp SRC GRP_CX_grp.Z0 DST GLB_A6_IN1.A0 GLB_A6_IN1B.A0 GLB_D6_IN14B.A0 GLB_D6_IN14.A0;
NET BX_grp SRC GRP_BX_grp.Z0 DST GLB_A6_IN11.A0 GLB_A6_IN11B.A0 GLB_D6_IN4B.A0 GLB_D6_IN4.A0;
NET D6_P0 SRC GLB_D6_P0.Z0 DST GLB_D6_P0_xa.A0;
NET D6_IN4 SRC GLB_D6_IN4.Z0 DST GLB_D6_P4.A2 GLB_D6_P0.A2;
NET D6_IN14 SRC GLB_D6_IN14.Z0 DST GLB_D6_P8.A1 GLB_D6_P0.A1;
NET D6_IN15 SRC GLB_D6_IN15.Z0 DST GLB_D6_P8.A0 GLB_D6_P4.A0 GLB_D6_P0.A0;
SYM PGAND3 GLB_A6_P13 GLB glb01;
PIN Z0 OUT A6_P13;
PIN A2 IN A6_IN0B;
PIN A1 IN A6_IN1;
PIN A0 IN A6_IN11B;
END; // SYM PGANDD3
SYM PGAND3 GLB_A6_P8 GLB glb01;
PIN Z0 OUT A6_P8;
PIN A2 IN A6_IN0B;
PIN A1 IN A6_IN1B;
PIN A0 IN A6_IN11;
END; // SYM PGANDD3
SYM PGAND3 GLB_A6_P4 GLB glb01;
PIN Z0 OUT A6_P4;
PIN A2 IN A6_IN0B;
PIN A1 IN A6_IN1;
PIN A0 IN A6_IN11;
END; // SYM PGANDD3
SYM PGAND3 GLB_A6_P0 GLB glb01;
PIN Z0 OUT A6_P0;
PIN A2 IN A6_IN0;
PIN A1 IN A6_IN1B;
PIN A0 IN A6_IN11B;
END; // SYM PGANDD3
SYM PGBUFI GLB_A6_G3 GLB glb01;
PIN Z0 OUT A6_G3;
PIN A0 IN GND;
END; // SYM PGORG1
SYM PGBUFI GLB_A6_G2 GLB glb01;
PIN Z0 OUT A6_G2;
PIN A0 IN GND;
END; // SYM PGORG1
SYM PGBUFI GLB_A6_G1 GLB glb01;
PIN Z0 OUT A6_G1;
PIN A0 IN GND;
END; // SYM PGORG1
SYM PGBUFI GLB_A6_G0 GLB glb01;
PIN Z0 OUT A6_G0;
PIN A0 IN GND;
END; // SYM PGORG1
SYM PGBUFI GLB_A6_P0_xa GLB glb01;
PIN Z0 OUT A6_P0_xa;
PIN A0 IN A6_P0;
END; // SYM PGBUFXA
SYM PGBUFI GLB_AND_731 GLB glb01;
PIN Z0 OUT AND_731;
PIN A0 IN A6_X3O;
END; // SYM PGBUFXO
SYM PGBUFI GLB_A6_P4_xa GLB glb01;
PIN Z0 OUT A6_P4_xa;
PIN A0 IN A6_P4;
END; // SYM PGBUFXA
SYM PGBUFI GLB_AND_732 GLB glb01;
PIN Z0 OUT AND_732;
PIN A0 IN A6_X2O;
END; // SYM PGBUFXO
SYM PGBUFI GLB_A6_P8_xa GLB glb01;
PIN Z0 OUT A6_P8_xa;
PIN A0 IN A6_P8;
END; // SYM PGBUFXA
SYM PGBUFI GLB_AND_733 GLB glb01;
PIN Z0 OUT AND_733;
PIN A0 IN A6_X1O;
END; // SYM PGBUFXO
SYM PGBUFI GLB_A6_P13_xa GLB glb01;
PIN Z0 OUT A6_P13_xa;
PIN A0 IN A6_P13;
END; // SYM PGBUFXA
SYM PGBUFI GLB_AND_734 GLB glb01;
PIN Z0 OUT AND_734;
PIN A0 IN A6_X0O;
END; // SYM PGBUFXO
SYM PGBUFI GLB_A6_IN11 GLB glb01;
PIN Z0 OUT A6_IN11;
PIN A0 IN BX_grp;
END; // SYM PGBUFI
SYM PGBUFI GLB_A6_IN1 GLB glb01;
PIN Z0 OUT A6_IN1;
PIN A0 IN CX_grp;
END; // SYM PGBUFI
SYM PGBUFI GLB_A6_IN0 GLB glb01;
PIN Z0 OUT A6_IN0;
PIN A0 IN AX_grp;
END; // SYM PGBUFI
SYM PGXOR2 GLB_A6_X3O GLB glb01;
PIN Z0 OUT A6_X3O;
PIN A1 IN A6_P0_xa;
PIN A0 IN A6_G0;
END; // SYM PGXOR2
SYM PGXOR2 GLB_A6_X2O GLB glb01;
PIN Z0 OUT A6_X2O;
PIN A1 IN A6_P4_xa;
PIN A0 IN A6_G1;
END; // SYM PGXOR2
SYM PGXOR2 GLB_A6_X1O GLB glb01;
PIN Z0 OUT A6_X1O;
PIN A1 IN A6_P8_xa;
PIN A0 IN A6_G2;
END; // SYM PGXOR2
SYM PGXOR2 GLB_A6_X0O GLB glb01;
PIN Z0 OUT A6_X0O;
PIN A1 IN A6_P13_xa;
PIN A0 IN A6_G3;
END; // SYM PGXOR2
SYM PGINVI GLB_A6_IN0B GLB glb01;
PIN ZN0 OUT A6_IN0B;
PIN A0 IN AX_grp;
END; // SYM PGINVI
SYM PGINVI GLB_A6_IN11B GLB glb01;
PIN ZN0 OUT A6_IN11B;
PIN A0 IN BX_grp;
END; // SYM PGINVI
SYM PGINVI GLB_A6_IN1B GLB glb01;
PIN ZN0 OUT A6_IN1B;
PIN A0 IN CX_grp;
END; // SYM PGINVI
SYM PGAND3 GLB_D6_P13 GLB glb00;
PIN Z0 OUT D6_P13;
PIN A2 IN D6_IN4B;
PIN A1 IN D6_IN14B;
PIN A0 IN D6_IN15B;
END; // SYM PGANDD3
SYM PGAND3 GLB_D6_P8 GLB glb00;
PIN Z0 OUT D6_P8;
PIN A2 IN D6_IN4B;
PIN A1 IN D6_IN14;
PIN A0 IN D6_IN15;
END; // SYM PGANDD3
SYM PGAND3 GLB_D6_P4 GLB glb00;
PIN Z0 OUT D6_P4;
PIN A2 IN D6_IN4;
PIN A1 IN D6_IN14B;
PIN A0 IN D6_IN15;
END; // SYM PGANDD3
SYM PGAND3 GLB_D6_P0 GLB glb00;
PIN Z0 OUT D6_P0;
PIN A2 IN D6_IN4;
PIN A1 IN D6_IN14;
PIN A0 IN D6_IN15;
END; // SYM PGANDD3
SYM PGBUFI GLB_D6_G3 GLB glb00;
PIN Z0 OUT D6_G3;
PIN A0 IN GND;
END; // SYM PGORG1
SYM PGBUFI GLB_D6_G2 GLB glb00;
PIN Z0 OUT D6_G2;
PIN A0 IN GND;
END; // SYM PGORG1
SYM PGBUFI GLB_D6_G1 GLB glb00;
PIN Z0 OUT D6_G1;
PIN A0 IN GND;
END; // SYM PGORG1
SYM PGBUFI GLB_D6_G0 GLB glb00;
PIN Z0 OUT D6_G0;
PIN A0 IN GND;
END; // SYM PGORG1
SYM PGBUFI GLB_D6_P0_xa GLB glb00;
PIN Z0 OUT D6_P0_xa;
PIN A0 IN D6_P0;
END; // SYM PGBUFXA
SYM PGBUFI GLB_AND_728 GLB glb00;
PIN Z0 OUT AND_728;
PIN A0 IN D6_X3O;
END; // SYM PGBUFXO
SYM PGBUFI GLB_D6_P4_xa GLB glb00;
PIN Z0 OUT D6_P4_xa;
PIN A0 IN D6_P4;
END; // SYM PGBUFXA
SYM PGBUFI GLB_AND_729 GLB glb00;
PIN Z0 OUT AND_729;
PIN A0 IN D6_X2O;
END; // SYM PGBUFXO
SYM PGBUFI GLB_D6_P8_xa GLB glb00;
PIN Z0 OUT D6_P8_xa;
PIN A0 IN D6_P8;
END; // SYM PGBUFXA
SYM PGBUFI GLB_AND_730 GLB glb00;
PIN Z0 OUT AND_730;
PIN A0 IN D6_X1O;
END; // SYM PGBUFXO
SYM PGBUFI GLB_D6_P13_xa GLB glb00;
PIN Z0 OUT D6_P13_xa;
PIN A0 IN D6_P13;
END; // SYM PGBUFXA
SYM PGBUFI GLB_AND_735 GLB glb00;
PIN Z0 OUT AND_735;
PIN A0 IN D6_X0O;
END; // SYM PGBUFXO
SYM PGBUFI GLB_D6_IN15 GLB glb00;
PIN Z0 OUT D6_IN15;
PIN A0 IN AX_grp;
END; // SYM PGBUFI
SYM PGBUFI GLB_D6_IN14 GLB glb00;
PIN Z0 OUT D6_IN14;
PIN A0 IN CX_grp;
END; // SYM PGBUFI
SYM PGBUFI GLB_D6_IN4 GLB glb00;
PIN Z0 OUT D6_IN4;
PIN A0 IN BX_grp;
END; // SYM PGBUFI
SYM PGXOR2 GLB_D6_X3O GLB glb00;
PIN Z0 OUT D6_X3O;
PIN A1 IN D6_P0_xa;
PIN A0 IN D6_G0;
END; // SYM PGXOR2
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