bf533_io.c

skyeye-1.2-RC7-3的源代码

}


void
uart_write_word (bu32 addr, bu16 data)
{
	bu32 offset = addr - UART_IO_START_ADDR;
	/*
	   if(offset != 0 && offset != 0xc)
	   printf("************offset=%x,value = %x\n",offset,data);
	 */
	switch (offset) {
	case 0x0:		// THR
		{
			unsigned char c = data & 0xff;
			/*There is no TSR ,so we set TEMT and THRE together */
			io.uart.lsr |= 0x60;
			io.sic.sic_isr &= ~0x8000;
			io.uart.iir = 0x1;
			write (skyeye_config.uart.fd_out, &c, 1);
		}
		break;
	case 0x4:		//FCR
		/*just walkaround code to open uart */
		if (io.uart.lcr & 0x80) {
			io.uart.dlh = data;
			/*
			   if(data&0x8){
			   printf("KSDBG:UART OPEN\n");
			   UART_OPEN = 1;
			   } */
		}
		else {
			io.uart.ier = data;
			/*generate RX interrupt */
			if (data & 0x1) {
			}
			/*generate TX interrupt */
			if (data & 0x2) {
			}
			if (data & 0x8) {
				UART_OPEN = 1;
			}
		}

		break;
	case 0xc:		// SCR
		io.uart.lcr = data;
		break;
	case 0x24:
		io.uart.gctl = data;
		break;
	default:
		IO_ERR;
		//printf("%c", data); fflush(stdout);
		DBG_PRINT ("uart_write(%s=0x%08x)\n", "uart_reg", addr);
		break;
	}
}
bu32
uart_read_long (bu32 addr)
{
	bu16 ret;
	IO_ERR;
	return ret;
}

void
uart_write_long (bu32 addr, bu32 value)
{
	IO_ERR;
	return;
}

bu8
uart_read_byte (bu32 addr)
{
	bu8 ret;
	IO_ERR;
	return ret;
}
static void
uart_write_byte (bu32 addr, bu8 value)
{
	IO_ERR;
	return;
}
static bu16
ebiu_read_word (bu32 addr)
{
	int offset = addr - EBIU_IO_START_ADDR;
	switch (offset) {
	case 0:
		return io.ebiu.amgctl;
	case 4:
		return io.ebiu.ambctl0;
	case 8:
		return io.ebiu.ambctl1;
	case 0x10:
		return io.ebiu.sdgctl;
	case 0x1c:
		return io.ebiu.sdstat;
	default:
		IO_ERR;
	}
	return;

}
static bu32
ebiu_read_long (bu32 addr)
{
	int offset = addr - EBIU_IO_START_ADDR;
	switch (offset) {
	case 0:
		return io.ebiu.amgctl;
	case 4:
		return io.ebiu.ambctl0;
	case 8:
		return io.ebiu.ambctl1;
	case 0x10:
		return io.ebiu.sdgctl;
	default:
		IO_ERR;
	}
	return;

}
static void
ebiu_write_long (bu32 addr, bu32 v)
{
	int offset = addr - EBIU_IO_START_ADDR;
	switch (offset) {
	case 0:
		io.ebiu.amgctl = v;
		break;
	case 4:
		io.ebiu.ambctl0 = v;
		break;
	case 8:
		io.ebiu.ambctl1 = v;
		break;
	case 0x10:
		io.ebiu.sdgctl = v;
		break;
	default:
		IO_ERR;
	}
	return;
}
static void
ebiu_write_word (bu32 addr, bu16 v)
{
	int offset = addr - EBIU_IO_START_ADDR;
	switch (offset) {
	case 0:
		io.ebiu.amgctl = v;
		break;
	case 4:
		io.ebiu.ambctl0 = v;
		break;
	case 8:
		io.ebiu.ambctl1 = v;
		break;
	case 0x18:
		io.ebiu.sdrrc = v;
		break;
	default:
		IO_ERR;
	}
	return;
}



static bu8
dma_read_byte (bu32 addr)
{
	IO_ERR;
	bu8 ret = 0;
	return ret;
}
static void
dma_write_byte (bu32 addr, bu8 value)
{
	IO_ERR;
	/*
	   int channel = addr&0x3c0;
	   int offset = (addr&0x3f)>>2;
	   io.dma.bf533_dma_channel[channel][offset] = value;
	 */
	return;
}


static bu16
dma_read_word (bu32 addr)
{
	bu16 ret;
	int channel = (addr & 0x3c0) >> 6;
	int offset = (addr & 0x3f) >> 2;
	ret = io.dma.bf533_dma_channel[channel][offset];
	return ret;
}
static void
dma_write_word (bu32 addr, bu16 value)
{
	int channel = (addr & 0x3c0) >> 6;
	int offset = (addr & 0x3f) >> 2;
	//printf("\nchannel=0x%x,offset = %x,value=%x\n",channel,offset,value);
	switch (offset) {
	case 0x2:
		/*CONFIG*/ io.dma.bf533_dma_channel[channel][offset] = value;
		if (channel == MDMA_D0) {

			unsigned long src =
				io.dma.bf533_dma_channel[MDMA_S0][START_ADDR];
			unsigned long dst =
				io.dma.bf533_dma_channel[MDMA_D0][START_ADDR];
			unsigned long size =
				io.dma.bf533_dma_channel[MDMA_D0][X_COUNT];
			//mem_cpy(start_addr,end_addr,size);

			/*work around code for dma copy to isram */
			if (dst >= 0xffa00000) {
				return;
			}
				/***************************************/
			fprintf (PF,
				 "DMA copy begin from 0x%x to 0x%x,size=0x%x\n",
				 src, dst, size);
			int i = size;
			for (; i >= 0; i--) {
				put_byte (saved_state.memory, dst++,
					  get_byte (saved_state.memory,
						    src++));
			}
			//printf()

		}
		break;

	default:
		io.dma.bf533_dma_channel[channel][offset] = value;
		break;
	}
	return;
}
static bu32
dma_read_long (bu32 addr)
{
	bu32 ret;
	int channel = (addr & 0x3c0) >> 6;
	int offset = (addr & 0x3f) >> 2;
	ret = io.dma.bf533_dma_channel[channel][offset];
	return ret;
}
static void
dma_write_long (bu32 addr, bu32 value)
{
	int channel = (addr & 0x3c0) >> 6;
	int offset = (addr & 0x3f) >> 2;
	//printf("\nchannel=0x%x,offset = %x,value=%x\n",channel,offset,value); 
	io.dma.bf533_dma_channel[channel][offset] = value;
	return;
}
static void
core_int_write_long (bu32 addr, bu32 v)
{
	int offset = addr - CORE_INT_IO_START_ADDR;
	//printf("%x,%x\n",addr,v);
	switch (offset) {
	case 0x104:
		io.core_int.imask = (v | 0x1f) & 0xffff;
		break;
	case 0x108:
		io.core_int.ipend = v;
		break;
	case 0x10c:
		io.core_int.ilat = v;
		//printf("write ilat %x\n",v);
		break;
	case 0x110:
		io.core_int.iprio = v;
		break;
	default:
		if (offset >= 0 && offset < 0x100) {
			io.core_int.evt[offset >> 2] = v;
			return;
		}
		IO_ERR;
	}
}
static bu32
core_int_read_long (bu32 addr)
{
	int offset = addr - CORE_INT_IO_START_ADDR;
	bu32 ret;
	//printf("read %x\n",offset);
	switch (offset) {
	case 0x104:
		ret = (io.core_int.imask | 0x1f) & 0xffff;
		break;
	case 0x108:
		ret = io.core_int.ipend;
		break;
	case 0x10c:
		ret = io.core_int.ilat;
		//printf("read ilat %x",ret);
		break;
	case 0x110:
		ret = io.core_int.iprio;
		break;
	default:
		if (offset >= 0 && offset < 0x100) {
			ret = io.core_int.evt[offset >> 2];
			return ret;
		}
		IO_ERR;

	}
	return ret;

}
static void
wd_write_word (bu32 addr, bu16 v)
{
	int offset = addr - WD_IO_START_ADDR;
	switch (offset) {
	case 0x0:
		io.wd.ctl = v;
		break;
	case 0x4:
		io.wd.cnt = v;
		break;
	case 0x8:
		io.wd.stat = v;
		break;
	default:
		IO_ERR;
	}
}



static bu32
deu_read_long (bu32 addr)
{
	int offset = addr - DEU_IO_START_ADDR;
	switch (offset) {
	case 0x0:
		return io.deu.dspid;
	default:
		IO_ERR;

	}
}

static bu16
dpmc_read_word (bu32 addr)
{
	int offset = addr - DPMC_IO_START_ADDR;
	bu16 ret;
	switch (offset) {
	case 0x0:
		ret = io.dpmc.pll_ctl;
		break;
	case 0x4:
		ret = io.dpmc.pll_div;
		break;
	case 0x8:
		ret = io.dpmc.vr_ctl;
		break;
	case 0xc:
		ret = io.dpmc.pll_stat;	/*PLL_LOCKED is set */
		break;
	case 0x10:
		ret = io.dpmc.pll_lockcnt;
		break;
	default:
		IO_ERR;
	}
	return ret;
}
static void
dpmc_write_word (bu32 addr, bu16 v)
{
	int offset = addr - DPMC_IO_START_ADDR;
	switch (offset) {
	case 0x0:
		io.dpmc.pll_ctl = v;
		break;
	case 0x4:
		io.dpmc.pll_div = v;
		break;
	case 0x8:
		io.dpmc.vr_ctl = v;
		break;
	case 0xc:
		io.dpmc.pll_stat = v;
		break;
	case 0x10:
		io.dpmc.pll_lockcnt = v;
		break;
	default:
		IO_ERR;
	}
	return;
}


static bu32
sic_read_long (bu32 addr)
{
	int offset = addr - SIC_IO_START_ADDR;
	bu32 ret;
	switch (offset) {
	case 0x0:
		ret = io.sic.swrst;
		break;
	case 0x4:
		ret = io.sic.syscr;
		break;
	case 0xc:
		ret = io.sic.sic_imask;
		//printf("read ret= %x\n",ret);
		break;
	case 0x20:
		ret = io.sic.sic_isr;
		//printf("read sic_isr 0x%x\n",ret);
		break;
	case 0x24:
		ret = io.sic.sic_iwr;
		break;
	default:
		if (offset >= 0x10 && offset <= 0x18) {
			ret = io.sic.sic_iar[(offset - 0x10) >> 2];
			return ret;
		}

		IO_ERR;
	}
	return ret;
}
static void
sic_write_long (bu32 addr, bu32 v)
{
	int offset = addr - SIC_IO_START_ADDR;
	switch (offset) {
	case 0x24:
		io.sic.sic_iwr = v;
		break;
	case 0xc:
		//printf("write v=%x\n",v);
		io.sic.sic_imask = v;
		break;

	default:
		if (offset >= 0x10 && offset <= 0x18) {
			io.sic.sic_iar[(offset - 0x10) >> 2] = v;
			return;
		}
		IO_ERR;
	}
}
static void
l1mem_write_long (bu32 addr, bu32 v)
{
	int offset = addr - L1MEM_IO_START_ADDR;
	int pos = offset >> 2;
	switch (pos) {
	default:
		io.l1mem.reg[pos] = v;
		break;
	}
}
static bu32
l1mem_read_long (bu32 addr)
{
	int offset = addr - L1MEM_IO_START_ADDR;
	int pos = offset >> 2;
	bu32 ret;
	switch (pos) {
	default:
		ret = io.l1mem.reg[pos];
	}
	return ret;
}
static void
l1dmem_write_long (bu32 addr, bu32 v)
{
	int offset = addr - L1DMEM_IO_START_ADDR;
	int pos = offset >> 2;
	switch (pos) {
	default:
		io.l1dmem.reg[pos];
		break;
	}
}
static void
rtc_write_word (bu32 addr, bu16 v)
{
	int offset = addr - RTC_IO_START_ADDR;
	printf ("offset=%x\n", offset);
	switch (offset) {
	case 0x4:
		io.rtc.ictl = v;
		return;
	case 0x14:
		io.rtc.pren = v;
		/*set write complete bit to one */
		io.rtc.istat |= 0x8000;
		return;
	case 0x8:
		io.rtc.istat = v;
		return;

	default:
		IO_ERR;
	}
}
static bu16
rtc_read_word (bu32 addr)
{
	int offset = addr - RTC_IO_START_ADDR;
	bu16 ret;
	switch (offset) {

	case 0x14:
		ret = io.rtc.pren;
		break;
	case 0x8:
		ret = io.rtc.istat;
		/*clear write complete bit */
		io.rtc.istat &= ~0x8000;
		break;
	default:
		IO_ERR;
	}
	return ret;

}
static void
rtc_write_long (bu32 addr, bu32 v)
{
	int offset = addr - RTC_IO_START_ADDR;
	switch (offset) {
	case 0x0:
		io.rtc.stat = v;
		return;
	case 0x10:
		io.rtc.alarm = v;
		return;
	default:
		IO_ERR;
	}
}
static bu32
rtc_read_long (bu32 addr)
{
	int offset = addr - RTC_IO_START_ADDR;
	bu32 ret;
	switch (offset) {
	case 0x0:
		ret = io.rtc.stat;
		break;
	default:
		IO_ERR;
	}
	return ret;
}
static bu32
l1dmem_read_long (bu32 addr)
{
	int offset = addr - L1DMEM_IO_START_ADDR;
	int pos = offset >> 2;
	bu32 ret;
	switch (pos) {
	default:
		ret = io.l1dmem.reg[pos];
		break;
	}
	return ret;
}
static void
core_timer_write_long (bu32 addr, bu32 v)
{
	int offset = addr - CORE_TIMER_IO_START_ADDR;
	//printf("offset=%x",offset);
	switch (offset) {
	case 0x0:
		io.core_timer.tcntl = v;
		/*not sure core_int is open at this time */
		if (io.core_timer.tcntl & 0x2) {
			io.core_int.imask |= 1 << CORE_TIMER_IRQ;
		}
		break;
	case 0x4:
		io.core_timer.tperiod = v;
		break;
	case 0x8:
		io.core_timer.tscale = v;
		break;
	case 0xc:
		io.core_timer.tcount = v;
		break;
	default:
		IO_ERR;
	}
	return;
}
static bu32
core_timer_read_long (bu32 addr)
{
	int offset = addr - CORE_TIMER_IO_START_ADDR;
	bu32 ret;
	switch (offset) {
	case 0x0:
		ret = io.core_timer.tcntl;
		break;
	case 0x4:
		ret = io.core_timer.tperiod;
		break;
	case 0x8:
		ret = io.core_timer.tscale;
		break;
	case 0xc:
		ret = io.core_timer.tcount;
		break;
	default:
		IO_ERR;
	}
	return ret;

}

static bu16
pf_read_word (bu32 addr)
{
	int offset = addr - PF_IO_START_ADDR;
	bu32 ret;
	switch (offset) {
	case 0x30:
		ret = io.pf.fio_dir;
		break;
	default:
		IO_ERR;
	}
	return ret;
}
static void
pf_write_word (bu32 addr, bu16 v)
{
	int offset = addr - PF_IO_START_ADDR;
	switch (offset) {
	case 0x4:
		io.pf.fio_flag_c = v;
		return;
	case 0x8:
		io.pf.fio_flag_s = v;
		return;
	case 0x30:
		io.pf.fio_dir = v;
		return;
	default:
		IO_ERR;
	}
}

void
init_bf533_mach (mach_t * p_mach)
{
	/*init io  value */
	io.dpmc.pll_div = 0x0005;
	io.dpmc.pll_ctl = 0x1400;
	io.dpmc.pll_lockcnt = 0x0200;
	io.dpmc.pll_stat = 0x00a2;
	//io.core_int.ipend = 0x10; /*at the beginning,global int is disabled*/
	io.core_int.imask = 0x1f;
	io.core_int.ilat = 0x0;
	 /**/ io.sic.sic_isr = 0x0;
	io.uart.lcr = 0x0;
	io.uart.dll = 0x0001;
	io.uart.ier = 0x0;
	io.uart.iir = 0x1;
	io.uart.lsr = 0x60;
	/*init mach */
	if (!p_mach) {
		skyeye_exit (-1);
	}
	p_mach->io_read_byte = bf533_io_read_byte;
	p_mach->io_read_word = bf533_io_read_word;
	p_mach->io_read_long = bf533_io_read_long;
	p_mach->io_write_byte = bf533_io_write_byte;
	p_mach->io_write_word = bf533_io_write_word;
	p_mach->io_write_long = bf533_io_write_long;
	p_mach->io_do_cycle = bf533_io_do_cycle;
	p_mach->disable_int = bf533_disable_int;
	p_mach->enable_int = bf533_enable_int;
	p_mach->clear_int = bf533_clear_int;
	p_mach->set_int = bf533_set_int;
	p_mach->sti = bf533_sti;
	p_mach->cli = bf533_cli;
}