skyeye_mach_s3c4510b.c

skyeye-1.2-RC7-3的源代码

/*
skyeye_mach_s3c4510b.c - define machine s3c4510b for skyeye
Copyright (C) 2003 Skyeye Develop Group
for help please send mail to <[e-mail]>

This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

*/
/*
* 06/20/2005	move ethernet simulation to dev_net_s3c4510b.c
* 		walimis <[e-mail]>
*
* 9/05/2004	add ethernet controller support.
*		get patch from <[e-mail]>
* 		walimis <[e-mail]>
*
* 10/05/2003	correct interrupt support. now it can boot uclinux to invoke shell.
* 		walimis <[e-mail]>
*
* 7/21/2003	correct timer support.
* 		now it can boot uclinux.
* 		walimis <[e-mail]>
*
* 7/17/2003	add interrupt, timer and uart support.
* 		walimis <[e-mail]>
*
* 3/28/2003 	init this file.
* 		add machine s3c4510b's function.Most taken from original armio.c
* 		include: s3c4510b_mach_init, s3c4510b_io_do_cycle
* 		s3c4510b_io_read_word, s3c4510b_io_write_word
*		walimis <[e-mail]>
*
* */
//koodailar add for mingw 2005.12.18 ----------------------------------------
#ifdef __MINGW32__
#include "arch/arm/common/armdefs.h"
#include "utils/stub/mingw_help.h"
#else
#include "armdefs.h"
#endif
// end ----------------------------------------------------------------------
#include "s3c4510b.h"
//zzc:2005-1-1
#ifdef __CYGWIN__
//chy 2005-07-28
#include <time.h>
//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
/*struct timeval
{
long tv_sec;
long tv_usec;
};*/
//AJ2D--------------------------------------------------------------------------

#endif /*  */
ARMword s3c4510b_io_read_word (ARMul_State * state, ARMword addr);
void s3c4510b_io_write_word (ARMul_State * state, ARMword addr, ARMword data);

/* s3c4510b Internal IO Registers
* */
typedef struct s3c4510b_io
{

	/*System Manager control */
	ARMword syscfg;
	ARMword clkcon;

	/*Interrupt Controller Registers */
	ARMword intmod;
	ARMword intpnd;
	ARMword intmsk;
	ARMword intoffset;
	ARMword intpndtst;
	ARMword intoset_fiq;
	ARMword intoset_irq;

	/*UART Registers */
	ARMword ulcon0;
	ARMword ulcon1;
	ARMword ucon0;
	ARMword ucon1;
	ARMword ustat0;
	ARMword ustat1;
	ARMword utxbuf0;
	ARMword utxbuf1;
	ARMword urxbuf0;
	ARMword urxbuf1;
	ARMword ubrdiv0;
	ARMword ubrdiv1;

	/*Timers Registers */
	ARMword tmod;
	ARMword tdata0;
	ARMword tdata1;
	int tcnt0;
	int tcnt1;
} s3c4510b_io_t;
static s3c4510b_io_t s3c4510b_io;

#define io s3c4510b_io
#define ENABLE_TIMER0 io.tmod & 0x1
#define ENABLE_TIMER1 io.tmod & 0x8

//extern int skyeye_net_on;
static unsigned char mac_buf[4096];
static void
s3c4510b_update_int (ARMul_State * state)
{
	ARMword requests = io.intpnd & (~io.intmsk & INT_MASK_INIT);
	state->NfiqSig = (requests & io.intmod) ? LOW : HIGH;
		state->NirqSig = (requests & ~io.intmod) ? LOW : HIGH;
		} static void
		s3c4510b_set_interrupt (unsigned int irq)
		{
			io.intpnd |= (1 << irq);
		} static int

		s3c4510b_pending_intr (u32 interrupt)
		{
			return ((io.intpnd & (1 << interrupt)));
		}
		static void
		s3c4510b_update_intr (void *mach)
		{
			struct machine_config *mc = (struct machine_config *) mach;
			ARMul_State *state = (ARMul_State *) mc->state;
			s3c4510b_update_int (state);
		} static void

		s3c4510b_io_reset (ARMul_State * state)
		{
			memset (&s3c4510b_io, 0, sizeof (s3c4510b_io));
			io.syscfg = 0x37ffff91;
			io.intmsk = INT_MASK_INIT;
			io.intoffset = io.intoset_fiq = io.intoset_irq = 0x00000054;
			io.ustat0 = io.ustat1 = 0xc0;
			io.tcnt0 = io.tcnt1 = 0xffffffff;
		};

		//koodailar add for mingw 2005.12.18 ----------------------------------------
		#ifdef __MINGW32__
		void
		s3c4510b_io_do_cycle (ARMul_State * state)
		{
			mingw_start_thread(skyeye_config.uart.fd_in);
			unsigned int t;
			fd_set rfds;
			struct timeval tv;
			int maxfd;

			/*Timer */
			if (ENABLE_TIMER0) {
				io.tcnt0--;
				if (io.tcnt0 < 0) {
					io.tcnt0 = io.tdata0;
					s3c4510b_set_interrupt (INT_TIMER0);
					s3c4510b_update_int (state);
					return;
				}
			}
			if (ENABLE_TIMER1) {
				if (--io.tcnt1 < 0) {
					io.tcnt1 = io.tdata1;
					s3c4510b_set_interrupt (INT_TIMER1);
					s3c4510b_update_int (state);
				}
			}
			/*UART*/ FD_SET (skyeye_config.uart.fd_in, &rfds);
			maxfd = skyeye_config.uart.fd_in;
			if (SDL_SemTryWait(get_mingw_read_sem())==0)
				{
					if(get_mingw_sem_first_time() != 1 && get_mingw_readed() == 1)
						{
							unsigned char buf;
							int n;
							n = 1;
							buf = get_mingw_char_read();
							set_mingw_readed(0);
							if (n > 0) {

								//ctrl_c support,replace by ctrl_a
								if (buf == 1)
									buf = 3;
									io.urxbuf0 = io.urxbuf1 = (int) buf;
									io.ustat0 |= UART_LSR_DR;
									io.ustat1 |= UART_LSR_DR;
									if (!(io.intpnd & (1 << INT_UARTRX0))
										|| !(io.intpnd & (1 << INT_UARTRX1))) {
											if ((io.ucon0 & 0x3) == 0x1) {
												s3c4510b_set_interrupt
												(INT_UARTRX0);
												s3c4510b_update_int (state);
												SDL_SemPost(get_mingw_read_sem());
												printf(" \b");
												fflush(stdout);
												return;
											}
											if ((io.ucon1 & 0x3) == 0x1) {
												s3c4510b_set_interrupt
												(INT_UARTRX1);
												s3c4510b_update_int (state);
												SDL_SemPost(get_mingw_read_sem());
												printf(" \b");
												fflush(stdout);
												return;
											}
										}
									}
								}
								SDL_SemPost(get_mingw_read_sem());
								printf(" \b");
								fflush(stdout);
							}
							s3c4510b_update_int (state);
						}
						#else
						/*s3c4510b io_do_cycle*/
						void
						s3c4510b_io_do_cycle (ARMul_State * state)
						{
							unsigned int t;
							fd_set rfds;
							struct timeval tv;
							int maxfd;

							/*Timer */
							if (ENABLE_TIMER0) {
								io.tcnt0--;
								if (io.tcnt0 < 0) {
									io.tcnt0 = io.tdata0;
									s3c4510b_set_interrupt (INT_TIMER0);
									s3c4510b_update_int (state);
									return;
								}
							}
							if (ENABLE_TIMER1) {
								if (--io.tcnt1 < 0) {
									io.tcnt1 = io.tdata1;
									s3c4510b_set_interrupt (INT_TIMER1);
									s3c4510b_update_int (state);
								}
							}
							/*UART*/ FD_SET (skyeye_config.uart.fd_in, &rfds);
							maxfd = skyeye_config.uart.fd_in;
							tv.tv_sec = 0;
							tv.tv_usec = 0;
							if (select (maxfd + 1, &rfds, NULL, NULL, &tv) > 0) {
								if (FD_ISSET (skyeye_config.uart.fd_in, &rfds)) {
									unsigned char buf;
									int n;
									n = read (skyeye_config.uart.fd_in, &buf, 1);
									if (n > 0) {

										//ctrl_c support,replace by ctrl_a
										if (buf == 1)
											buf = 3;
											io.urxbuf0 = io.urxbuf1 = (int) buf;
											io.ustat0 |= UART_LSR_DR;
											io.ustat1 |= UART_LSR_DR;
											if (!(io.intpnd & (1 << INT_UARTRX0))
												|| !(io.intpnd & (1 << INT_UARTRX1))) {
													if ((io.ucon0 & 0x3) == 0x1) {
														s3c4510b_set_interrupt
														(INT_UARTRX0);
														s3c4510b_update_int (state);
														return;
													}
													if ((io.ucon1 & 0x3) == 0x1) {
														s3c4510b_set_interrupt