📄 beacon.lst
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225 4 // PROCESS BEACON FRAME
226 4 // source address = destination address, 0xCC means beacon beacon frame
227 4 if ((plc_frame[0]==plc_frame[2])&&(plc_frame[1]==plc_frame[3])&& (plc_frame[4]==0xcc))
228 4 {
229 5
230 5 // clear the rx_timer, start it once process finished
231 5 disable_beacon_rx_timer();
232 5
233 5 if(flag_first_frame == 0)
234 5 {
235 6 average_ea = read_reg(0XEA);
236 6 average_eb = read_reg(0xEB);
237 6 flag_first_frame = 1; // clear first frame flag
238 6 }
239 5 else
240 5 {
C51 COMPILER V7.50 BEACON 11/12/2005 01:18:45 PAGE 5
241 6 average_ea = (average_ea + read_reg(0XEA))>>1;
242 6 average_eb = (average_eb + read_reg(0xEB))>>1;
243 6 }
244 5
245 5 success_received_frame++;
246 5
247 5 // Synchrnize the rx_count with tx_count
248 5 beacon_rx_frame_count = plc_frame[6];
249 5
250 5 uart_sendchar(0x99);
251 5
252 5 for(i=0;i<18;i++)
253 5 {
254 6 uart_sendchar(plc_frame[i]);
255 6 }
256 5
257 5 uart_sendchar(average_ea);
258 5 uart_sendchar(average_eb);
259 5 uart_sendchar(success_received_frame);
260 5
261 5 // once successfully receive a frame, start up rx timer, if tx timer out
262 5 // still not receive another frame, excute beacon_rx_time_out()
263 5 if (beacon_rx_frame_count!= BEACON_RX_FRAME_COUNT-1)
264 5 {
265 6 enable_beacon_rx_timer();
266 6 }
267 5 }
268 4
269 4 // read out link table. 00 00 is source address.
270 4 // to read out the table, FF as read command
271 4 if ((plc_frame[0]==0x00)&&(plc_frame[1]==0x00)&&(plc_frame[2]==local_address_R)&&(plc_frame[3]==local_
-address_L)&&(plc_frame[4]==0xFF))
272 4 {
273 5 send_table();
274 5 }
275 4
276 4 // clear the table, C0 as clear table command. When finish clear table
277 4 // use C1 to reply
278 4 if ((plc_frame[0]==0x00)&&(plc_frame[1]==0x00)&&(plc_frame[2]==local_address_R)&&(plc_frame[3]==local_
-address_L)&&(plc_frame[4]==0xC0))
279 4 {
280 5 clear_table();
281 5
282 5 // send back the ACK to confirm table is cleared. CMD 0xC1
283 5 plc_frame[0] = local_address_R;
284 5 plc_frame[1] = local_address_L;
285 5 plc_frame[2] = 0x00;
286 5 plc_frame[3] = 0x00;
287 5 plc_frame[4] = 0xC1;
288 5
289 5 sync_sendchar(BUFFER_WR_TXBUF);
290 5 send_block(plc_frame, 18);
291 5 send();
292 5 while (TX_BUSY == 0); // wait tx finish
293 5 }
294 4
295 4 // change register value through power line
296 4 // the command is 0xC2, repeat the command three times to gerantee no mistakes happen
297 4
298 4 if ((plc_frame[0]==0x00)&&(plc_frame[1]==0x00)&&(plc_frame[2]==local_address_R)&&(plc_frame[3]==local_
-address_L)&&(plc_frame[4]==0xc2)&&(plc_frame[8]==0xc2)&&(plc_frame[12]==0xc2))
299 4 {
C51 COMPILER V7.50 BEACON 11/12/2005 01:18:45 PAGE 6
300 5 // check whether the repeated 3 times value are the same.
301 5 if((plc_frame[5]==plc_frame[9])&&(plc_frame[5]==plc_frame[13])&&(plc_frame[6]==plc_frame[10])&&(plc_f
-rame[6]==plc_frame[14]))
302 5 {
303 6
304 6 EA = 0; // disable all interrupt when writing flash
305 6 FLASH_WriteByte((int code *)®_setting[0], plc_frame[5]);
306 6 FLASH_WriteByte((int code *)®_setting[1], plc_frame[6]);
307 6 EA = 1; // enable all interrupt after finishing writing flash
308 6
309 6 // send back the ACK to confirm the register write is finished. CMD 0xC3
310 6 plc_frame[0] = local_address_R;
311 6 plc_frame[1] = local_address_L;
312 6 plc_frame[2] = 0x00;
313 6 plc_frame[3] = 0x00;
314 6 plc_frame[4] = 0xC3;
315 6 plc_frame[8] = 0xC3;
316 6 plc_frame[12] = 0xC3;
317 6
318 6 // delay for several ms before send reply
319 6 for(i=0;i<250;i++)
320 6 for(j=0;j<250;j++);
321 6
322 6 sync_sendchar(BUFFER_WR_TXBUF);
323 6 send_block(plc_frame, 18);
324 6 send();
325 6 while (TX_BUSY == 0); // wait tx finish
326 6 }
327 5 else
328 5 {
329 6 // if command not correct, reply with cmd 0xC4
330 6 plc_frame[0] = local_address_R;
331 6 plc_frame[1] = local_address_L;
332 6 plc_frame[2] = 0x00;
333 6 plc_frame[3] = 0x00;
334 6 plc_frame[4] = 0xC4;
335 6 plc_frame[8] = 0xC4;
336 6 plc_frame[12] = 0xC4;
337 6
338 6 // delay for several ms before send reply
339 6 for(i=0;i<250;i++)
340 6 for(j=0;j<250;j++);
341 6
342 6 sync_sendchar(BUFFER_WR_TXBUF);
343 6 send_block(plc_frame, 18);
344 6 send();
345 6 while (TX_BUSY == 0); // wait tx finish
346 6 }
347 5
348 5 uart_sendblock(plc_frame,18);
349 5 }
350 4 RXOK = 1;
351 4 }
352 3 }
353 2
354 2 // ********* once beacon rx finish, write to flash
355 2 if (beacon_rx_frame_count == BEACON_RX_FRAME_COUNT-1)
356 2 {
357 3
358 3 disable_beacon_rx_timer();
359 3
360 3 // intialize min_ea to search
C51 COMPILER V7.50 BEACON 11/12/2005 01:18:45 PAGE 7
361 3 min_ea = 200;
362 3
363 3 // search for min_ea in the table, if meet the first 0, point to it
364 3 for(i=0;i<BEACON_TABLE_NM;i++)
365 3 {
366 4 if(min_ea > link_status_1[i].average_ea)
367 4 {
368 5 min_ea = link_status_1[i].average_ea;
369 5 wr_ea_index = i;
370 5 }
371 4
372 4 if(min_ea==0) break;
373 4 }
374 3
375 3 uart_sendchar(min_ea);
376 3 uart_sendchar(wr_ea_index);
377 3
378 3 // if new ea > min_ea, prepare to write into table
379 3 if(average_ea > min_ea)
380 3 {
381 4 // check whether this frame from a new address?
382 4 // if no, replace old one in table
383 4 for(i=0;i<BEACON_TABLE_NM;i++)
384 4 {
385 5 if((plc_frame[0]==link_status_1[i].address_R)&&(plc_frame[1]==link_status_1[i].address_L))
386 5 {
387 6 // set wr_ea_in
388 6 wr_ea_index = i;
389 6 }
390 5 }
391 4
392 4 // write the new frame info into table, at the position of wr_ea_index
393 4 EA = 0;
394 4 write_table(wr_ea_index, plc_frame[0], plc_frame[1], average_ea, average_eb,success_received_frame);
395 4 EA = 1;
396 4 }
397 3
398 3 // reset parameters for a new batch of
399 3 average_ea = 0;
400 3 average_eb = 0;
401 3 beacon_rx_frame_count = 0;
402 3 success_received_frame = 0;
403 3 flag_first_frame = 0; // set at 0 to indicate the first frame for next node.
404 3
405 3 }
406 2 }
407 1 }
408
409
410 // Beacon rx timer setup
411 void beacon_rx_time_out()
412 {
413 1 disable_beacon_rx_timer();
414 1
415 1 beacon_rx_frame_count++;
416 1
417 1 /* set up timer seconds again. */
418 1 enable_beacon_rx_timer();
419 1
420 1 }
421
422 void enable_beacon_rx_timer(void)
C51 COMPILER V7.50 BEACON 11/12/2005 01:18:45 PAGE 8
423 {
424 1 beacon_rx_timer_count = 0;
425 1 beacon_rx_timer_enable = 1;
426 1 }
427
428 void disable_beacon_rx_timer(void)
429 {
430 1 beacon_rx_timer_count = 0;
431 1 beacon_rx_timer_enable = 0;
432 1 }
433
434 void write_table(unsigned char i, unsigned char add_R, unsigned char add_L, unsigned char ave_ea, unsigned
- char ave_eb,unsigned char succ_rate)
435 {
436 1 // RXOK=0;
437 1
438 1 EA = 0; // disable all interrupt when writing flash
439 1 FLASH_WriteByte((int code *)&link_status_1[i].address_R, add_R);
440 1 FLASH_WriteByte((int code *)&link_status_1[i].address_L, add_L);
441 1 FLASH_WriteByte((int code *)&link_status_1[i].average_ea, ave_ea);
442 1 FLASH_WriteByte((int code *)&link_status_1[i].average_eb, ave_eb);
443 1 FLASH_WriteByte((int code *)&link_status_1[i].success_rate, succ_rate);
444 1 EA = 1; // enable all interrupt after finishing writing flash
445 1
446 1 // for debug
447 1 uart_sendchar(0xEE);
448 1 uart_sendchar(0xEE);
449 1 uart_sendchar(0xEE);
450 1 uart_sendchar(0xEE);
451 1
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