fangbo.vhd

来自「这是正玹实现代码,通过LUT来实现的!!!比其他要简单的多!还有方波,三角波的不」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity fangbo is
    port(clk:in std_logic;
         dout:out std_logic);
end fangbo;

architecture behav of fangbo is
begin
  process(clk)
  variable count:std_logic_vector(3 downto 0);
  variable flag:boolean;
  begin
      if clk'event and clk='0' then
  		 count:=count+1;
	  if count="1111" then
		 flag:=not flag;
 	  end if;
	  case flag is
when false=>dout<='1';
when true=>dout<='0';
         end case;
      end if;
   end process;
end behav;