suart.vhd

信号采集与频谱分析电路

-- SUART Project
-- 
-- SUART.vhd
-- SUART主模块
--
-- GW48-CK + GW-DSP/VGA (EP1K50TC144-3) 
-- 模式：No.1
-- Note: 1、需连接串口电缆
-- 		 2、跳线JMCU跳为：PIO31－P3.0，PIO30－P3.1
--		 3、时钟Clock0接为12MHz
--		 4、
--		 4、键1为rst（复位），正常测试时应置1
--
-- Design By jy2010
-- Update:
-- 		19/12/2002 归档
--

library	ieee;
use	ieee.std_logic_1164.all;

ENTITY suart IS
	PORT(
		clk		: IN std_logic;   
  		resetL	: IN std_logic;   
  		bclk	: OUT std_logic;   

  		-- Trasmitter
	  	txd		: OUT std_logic;   
	  	xbuf	: IN std_logic_vector(7 DOWNTO 0);   
	  	xmit_cmd	: IN std_logic;   
	  	xmit_done	: OUT std_logic;   

	  	-- Receiver
		rxd		: IN std_logic;   
		rbuf	: OUT std_logic_vector(7 DOWNTO 0);   
  		rec_ready	: OUT std_logic);   
END suart;

ARCHITECTURE top OF suart IS

	COMPONENT u_baud
		PORT(
			clk		: IN  std_logic;
			resetL	: IN  std_logic;
			bclk	: OUT std_logic);
	END COMPONENT;

	COMPONENT u_rec
		PORT(
			resetL	: IN  std_logic;
			bclk	: IN  std_logic;
			rxd		: IN  std_logic;
			rbuf	: OUT std_logic_vector(7 DOWNTO 0);
			rec_ready	: OUT std_logic);
	END COMPONENT;

	COMPONENT u_xmit
		PORT(
			resetL	: IN  std_logic;
			clk		: in  std_logic;
			bclk	: IN  std_logic;
			txd		: OUT std_logic;
			xbuf	: IN  std_logic_vector(7 DOWNTO 0);
			xmit_cmd	: IN  std_logic;
			xmit_done	: OUT std_logic);
	END COMPONENT;


	SIGNAL bclk_t	:  std_logic;   

BEGIN
	-- system connections
	-- uart

	bclk <= bclk_t;
	
	-- Instantiate the Transmitter
	iXMIT : u_xmit 
		PORT MAP (
			resetL 	=> resetL,
			clk 	=> clk,
			bclk 	=> bclk_t,
			txd 	=> txd,
			xbuf 	=> xbuf,
			xmit_cmd 	=> xmit_cmd,
			xmit_done 	=> xmit_done);   
	
	-- Instantiate the Receiver
	iREC : u_rec 
		PORT MAP (
			resetL 	=> resetL,
			bclk 	=> bclk_t,
			rxd 	=> rxd,
			rbuf 	=> rbuf,
			rec_ready 	=> rec_ready);   
	
	-- Instantiate the Baud Rate Generator
	iBAUD : u_baud 
		PORT MAP (
			clk 	=> clk,
			resetL 	=> resetL,
			bclk	=> bclk_t);   
	
END top;