u_xmit.vhd

信号采集与频谱分析电路

-- SUART Project
-- 
-- U_XMIT.vhd
-- 发送模块
--
-- Design By jy2010
-- Update:
-- 		19/12/2002 归档


library	ieee;
use	ieee.std_logic_1164.all;
use	ieee.std_logic_arith.all;
use	ieee.std_logic_unsigned.all;

ENTITY u_xmit IS
	generic	(FrameLen :	integer	:= 8 );
	PORT(
		clk		: in std_logic; -- 系统时钟
  		bclk	: IN std_logic;	-- UART工作时钟，16倍于波特率
		resetL	: IN std_logic;	-- 异步复位

  		txd		: OUT std_logic;	-- UART发送引脚   
  		xbuf	: IN std_logic_vector(FrameLen-1 DOWNTO 0);	-- 待发送数据   
  		xmit_cmd	: IN std_logic;		-- 发送命令，高电平有效，持续一个clk周期以上   
  		xmit_done	: OUT std_logic		-- 发送完成信号
		);   
END u_xmit;

ARCHITECTURE behv OF u_xmit IS

	-- Xmitter 状态机状态定义
	type	x_state_type is (x_IDLE,x_START,x_WAIT,x_SHIFT,x_STOP);
	SIGNAL next_state,state	:  x_state_type;   
	
	SIGNAL partoser 	:  std_logic_vector(FrameLen-1 DOWNTO 0);   
	SIGNAL partoser_ld	:  std_logic;   
	SIGNAL xShift_En 	:  std_logic;   

	SIGNAL xcnt16		:  std_logic_vector(4 DOWNTO 0);   
	SIGNAL xcnt16_en 	:  std_logic;   
	SIGNAL xcnt16_clr	:  std_logic;   

	SIGNAL xbitcnt 		:  std_logic_vector(3 DOWNTO 0);   
	SIGNAL xbitcnt_en	:  std_logic;   
	
	SIGNAL xmit_doneIn	:  std_logic;   
	SIGNAL xmit_cmd_p	:  std_logic;

BEGIN

process(clk,xmit_cmd)			-- 发送命令检测
begin
	if(clk'event and clk = '1') then
		if(xmit_cmd_p = '0' and xmit_cmd = '1') then
			xmit_cmd_p <= '1';
		elsif(xmit_cmd_p <= '1' and xcnt16_en 	= '1') then
			xmit_cmd_p <= xmit_cmd; 
		end if;	
	end if;
end process;

-- 16×计数器
PROCESS(bclk,resetL)
BEGIN
	IF (resetL = '0') THEN
		xcnt16 <= (others => '0');    
	ELSIF(bclk'EVENT AND bclk = '1') THEN
		IF (xcnt16_en = '1') THEN
			xcnt16 <= xcnt16 + 1;    
		ELSE
			xcnt16 <= (others => '0');    
		END IF;
	END IF;
END PROCESS;

-- 发送移位寄存器，低位先移出
PROCESS(bclk,resetL)
BEGIN
	IF (resetL = '0') THEN
		partoser <= (others => '0');    
	ELSIF(bclk'EVENT AND bclk = '1') then
		IF (partoser_ld = '1') THEN
			partoser <= xbuf;    
		ELSE
			IF (xShift_En = '1') THEN
				partoser <= '1' &  partoser(FrameLen-1 DOWNTO 1);    
			END IF;
		END IF;
	END IF;
END PROCESS;

-- 发送位计数器
PROCESS(bclk,resetL)
BEGIN
	IF (resetL = '0') THEN
		xbitcnt <= "0000";    
	ELSIF(bclk'EVENT AND bclk = '1') THEN
		IF (xcnt16_clr = '1') THEN
			xbitcnt <= "0000";    
		ELSIF (xbitcnt_en = '1') THEN
			xbitcnt <= xbitcnt + 1;    
		END IF;
	END IF;
END PROCESS;

-- STATE MACHINE
PROCESS(bclk,resetL)
BEGIN
	IF (resetL = '0') THEN
		state <= x_IDLE;
	ELSIF(bclk'EVENT AND bclk = '1') THEN
		state <= next_state;
	END IF;
END PROCESS;

-- 发送状态机
PROCESS(state,xmit_cmd_p,xcnt16,xbitcnt,partoser)
BEGIN
   
	-- Defaults
	xcnt16_en <= '0';    
	xcnt16_clr <= '0';    
	xbitcnt_en <= '0';    
	xmit_doneIn <= '0';    
	partoser_ld <= '0';
	xShift_En <= '0';

	case (state) is
		-- x_IDLE
		-- 等待发送命令
		WHEN x_IDLE =>
			txd <= '1';    
			IF (xmit_cmd_p = '1') THEN
				next_state <= x_START;    
				partoser_ld <= '1';    
			ELSE			
				next_state <= x_IDLE;    
				xcnt16_clr <= '1';    
				xmit_doneIn <= '1';    
			END IF;

		-- x_START
		WHEN x_START =>
			txd <= '0';
			IF (xcnt16 = "01111") THEN
				next_state <= x_WAIT;    
			ELSE
				next_state <= x_START;    
				xcnt16_en <= '1'; 	-- 16×计数使能   
			END IF;

		-- x_WAIT
		WHEN x_WAIT =>
			txd <= partoser(0);    
			IF (xcnt16 = "01110") THEN
				IF (xbitcnt = conv_std_logic_vector(conv_unsigned(FrameLen,4), 4)) THEN
					next_state <= x_STOP;    
				ELSE
					next_state <= x_SHIFT;    
					xbitcnt_en <= '1';	--发送位计数器使能   
				END IF;
			ELSE
				next_state <= x_WAIT;    
				xcnt16_en <= '1';    
			END IF;

		-- x_SHIFT
		WHEN x_SHIFT =>
			txd <= partoser(0);    
			xShift_En <= '1';    
			next_state <= x_WAIT;    
  
		-- x_STOP 发送stop bit
		WHEN x_STOP =>
			txd <= '1';    
			IF (xcnt16 = "01111" and xmit_cmd_p = '0') THEN
				next_state <= x_IDLE;    
				xmit_doneIn <= '1';    
			ELSE
				next_state <= x_STOP;    
				xcnt16_en <= '1';	
			END IF;

		WHEN OTHERS  =>
			txd <= '1';    
			next_state <= x_IDLE;    
	END CASE;
end process;


-- 发送完成信号
PROCESS(bclk,resetL)
BEGIN
	IF (resetL = '0') THEN
		xmit_done <= '0';    
	ELSIF(bclk'EVENT AND bclk = '1') THEN
		xmit_done <= xmit_doneIn;    
	END IF;
END PROCESS;

end behv;