adsuart.vhd

信号采集与频谱分析电路

library	ieee;
use ieee.std_logic_1164.all;
use	ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adsuart is
	port( clk	: in	std_logic;	-- 12MHz Clock 输入；UART模块使用
	     clk1	: in    std_logic;	-- 12MHz Clock 输入；ADS_SRAM模块使用
		rst	: in	std_logic;		-- 系统复位
		txd	: out	std_logic;		-- UART发送端
		rxd	: in	std_logic;		-- UART接收端
		AD_CLK	: out	std_logic;
		d		: in	std_logic_vector(7 downto 0));	-- 8位A/D数据
end adsuart;
architecture statemachine of adsuart is
	component suart
		PORT(clk, resetL	: IN std_logic;   
	  		bclk	: OUT std_logic;   
		  	txd			: OUT std_logic;   
		  	xmit_cmd	: IN std_logic;   
		  	xbuf		: IN std_logic_vector(7 DOWNTO 0);   
		  	xmit_done	: OUT std_logic;   
			rxd			: IN std_logic;   
			rbuf		: OUT std_logic_vector(7 DOWNTO 0);   
	  		rec_ready	: OUT std_logic);   
	END component;
	component adsram
		port(
			rst		: in	std_logic;	-- 复位
			clk1	: in	std_logic;	-- 50MHz Clock 输入；
			d		: in	std_logic_vector(7 downto 0);	-- 8位A/D数据
			q		: out	std_logic_vector(7 downto 0);	-- RAM 数据总线
			ramrden	: in	std_logic;
			ramrdck	: in	std_logic;
			rstaddr	: in	std_logic);
	end component;
	constant framecnt_coef :	integer := 9;
	constant adsendtime_coef :	integer := 11;
    signal	start : std_logic;		-- 当 mode=1 时 start 为单次采集启动
	signal	mode  : std_logic;		-- mode=1 : 单次采集 mode=0 : 连续采集
	signal	framecnt	: std_logic_vector(9 downto 0);		-- 帧计数器
	signal	uart_clk	: std_logic;						-- 来自波特率发生器
	signal	xmit_startH	: std_logic;						-- UART发送启动
	signal	xmit_doneH	: std_logic;						-- UART发送完成
	signal	xdata		: std_logic_vector(7 downto 0);		-- UART发送的数据（8位）
	signal	rec_readyH	: std_logic;						-- UART接收准备好
	signal	sramdata	: std_logic_vector(7 downto 0);		
	signal	fcntadd		: std_logic;
	signal	xmit_startH_t	: std_logic;
	signal	rdata		: std_logic_vector(7 downto 0);
	type	f_state is (start_s,start_AD_s,sample_AD_s,stop_AD_s,f_start_s,f_ready_s,f_data_s,f_end_s,again_tx_s);
	signal	next_state,state	: f_state;
	-- +++++++++++++++++++++++++++++++++++++++++++++++
	signal	adsdisp		: std_logic_vector(7 downto 0);
	signal	ramrden		: std_logic;						-- RAM读出使能
	signal	ramrdck		: std_logic;						-- RAM读出地址计数脉冲
	signal	rstaddr		: std_logic;						-- RAM地址复位
	signal	rstcount	: std_logic;
	signal	adendtime	: std_logic_vector(adsendtime_coef-1 downto 0);	-- A/D转换时间控制
	signal	framenum	: std_logic_vector(4 downto 0);		-- 帧数 （Default：1）
	signal	ramq		: std_logic_vector(7 downto 0);
	
begin
start<='0' ;  mode<='1'; 
	iUART : suart PORT MAP(clk=>clk, resetL=>rst, bclk=>uart_clk,		
		  		-- Trasmitter
			  	txd=>txd, 	xmit_cmd=>xmit_startH, 	xbuf=>xdata, xmit_done=>xmit_doneH,		
			  	-- Receiver
				rxd	=>rxd, rbuf=>rdata,	rec_ready=>rec_readyH);
	iadc : adsram
		port map(rst=>rst,	clk1=>clk1,	d=> d,	q=> ramq, ramrden=> ramrden,ramrdck=> ramrdck, rstaddr=> rstaddr);
process(clk1,rstcount,rst)
begin
	if(rstcount = '1' or rst = '0') then adendtime <= (others => '0');
	elsif(clk1'event and clk1 = '1') then adendtime <= adendtime + 1;	end if;
end process;
-- ADSUART 控制主状态机
process(state,start,uart_clk,mode)
begin
	if(uart_clk'event and uart_clk = '1') then
		case(state) is
			when start_s =>	ramrden <= '1';	rstaddr <= '1' ; rstcount <= '1'; ramrdck <= '0'; xmit_startH <= '0';
							if(start = '1' or mode = '1') then next_state <= start_AD_s;
							else next_state <= start_s;
							end if;
			when start_AD_s => 	ramrden <= '0';	-- 启动A/D
								rstaddr <= '1';	rstcount <= '0';
								if(adendtime >= 32) then next_state <= sample_AD_s;
								else next_state <= start_AD_s;	end if;
			when sample_AD_s => ramrden <= '0';	-- A/D采样
								rstaddr <= '0'; rstcount <= '0';
								if(adendtime >= 2000) then	next_state <= stop_AD_s;
								else next_state <= sample_AD_s;	end if;
			when stop_AD_s =>	ramrden <= '1';	-- A/D停止
								rstaddr <= '0';	rstcount <= '1'; xmit_startH <= '0'; next_state <= f_start_s;
			when f_start_s =>	rstaddr <= '1';	-- 帧发送开始，帧头：0x00
								rstcount <= '0'; xdata <= "00000000"; xmit_startH <= '1'; ramrdck <= '0'; next_state <= f_ready_s;	
			when f_ready_s =>	xmit_startH <= '0';	-- 等待发送完成
								rstcount <= '0'; rstaddr <= '0'; ramrdck <= '0'; fcntadd <= '0';
								if(xmit_doneH = '1') then
									if(framecnt(framecnt_coef) = '1') then	next_state <= f_end_s;
									else
										if(ramq = "11111111") then	xdata <= "11111110";
										elsif(ramq = "00000000") then	xdata <= "00000001";
										else xdata <= ramq;	end if;
										next_state <= f_data_s;
									end if;
								else next_state <= f_ready_s;	end if;
			when f_data_s => 	fcntadd <= '1' ;-- P55 AND (NOT P125) ;--'1';		-- 数据发送
								xmit_startH <= '1';	ramrdck <= '1';--
								next_state <= f_ready_s;
        	when f_end_s  =>	fcntadd <= '1';		-- 帧发送结束，帧尾：0xFF
								xdata <= "11111111"; xmit_startH <= '1';
								next_state <= again_tx_s;
			when again_tx_s =>	xmit_startH <= '0';	-- 发送结束判断
								if(xmit_doneH = '1') then
									if(framenum >= 1) then	next_state <= start_s;
									else    next_state <= f_start_s;
									end if;
								else next_state <= again_tx_s;
								end if;
			when others	=> 	next_state <= start_s;
		end case;
	end if;
end process;
process(rst,rstcount,fcntadd)			-- 帧长、帧数控制
begin
	if(rst = '0' or rstcount = '1') then framecnt <= conv_std_logic_vector(0,10); framenum <= conv_std_logic_vector(0,5);
	elsif(fcntadd'event and fcntadd = '1') then
		if(framecnt(framecnt_coef) = '1') then framecnt <= (others => '0');	framenum <= framenum + 1;
		else framecnt <= framecnt + 1; end if;
	end if;
end process;
process(uart_clk,rst)
begin
	if(rst = '0') then	state <= start_s;
	elsif(uart_clk'event and uart_clk = '1') then state <= next_state;	end if;
end process;
AD_CLK<=clk1;
end statemachine;