reserv.map.eqn

采用高速A/D的存储示波器设计

--operation mode is arithmetic

QB1L01 = AMPP_FUNCTION(QB1_safe_q[4], QB1L8);


--QB1_safe_q[5] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[5]
--operation mode is arithmetic

QB1_safe_q[5] = AMPP_FUNCTION(A1L51, QB1_safe_q[5], PB1L81, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L01);

--QB1L21 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella5~COUT
--operation mode is arithmetic

QB1L21 = AMPP_FUNCTION(QB1_safe_q[5], QB1L01);


--QB1_safe_q[6] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[6]
--operation mode is arithmetic

QB1_safe_q[6] = AMPP_FUNCTION(A1L51, QB1_safe_q[6], PB1L91, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L21);

--QB1L41 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella6~COUT
--operation mode is arithmetic

QB1L41 = AMPP_FUNCTION(QB1_safe_q[6], QB1L21);


--QB1_safe_q[7] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[7]
--operation mode is arithmetic

QB1_safe_q[7] = AMPP_FUNCTION(A1L51, QB1_safe_q[7], PB1L02, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L41);

--QB1L61 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella7~COUT
--operation mode is arithmetic

QB1L61 = AMPP_FUNCTION(QB1_safe_q[7], QB1L41);


--QB1_safe_q[8] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[8]
--operation mode is arithmetic

QB1_safe_q[8] = AMPP_FUNCTION(A1L51, QB1_safe_q[8], PB1L12, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L61);

--QB1L81 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella8~COUT
--operation mode is arithmetic

QB1L81 = AMPP_FUNCTION(QB1_safe_q[8], QB1L61);


--QB1_safe_q[9] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[9]
--operation mode is normal

QB1_safe_q[9] = AMPP_FUNCTION(A1L51, QB1_safe_q[9], PB1L22, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L81);


--DIN[6] is DIN[6]
--operation mode is normal

DIN[6]_lut_out = ADIN[6];
DIN[6] = DFFEA(DIN[6]_lut_out, CLK, VCC, , , , );


--PB1_ram_rom_data_reg[6] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]
--operation mode is normal

PB1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[7], NB1_q_b[6], PB1L01, VCC, PB1L9);


--DIN[5] is DIN[5]
--operation mode is normal

DIN[5]_lut_out = ADIN[5];
DIN[5] = DFFEA(DIN[5]_lut_out, CLK, VCC, , , , );


--PB1_ram_rom_data_reg[5] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]
--operation mode is normal

PB1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[6], NB1_q_b[5], PB1L01, VCC, PB1L9);


--DIN[4] is DIN[4]
--operation mode is normal

DIN[4]_lut_out = ADIN[4];
DIN[4] = DFFEA(DIN[4]_lut_out, CLK, VCC, , , , );


--PB1_ram_rom_data_reg[4] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]
--operation mode is normal

PB1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[5], NB1_q_b[4], PB1L01, VCC, PB1L9);


--DIN[3] is DIN[3]
--operation mode is normal

DIN[3]_lut_out = ADIN[3];
DIN[3] = DFFEA(DIN[3]_lut_out, CLK, VCC, , , , );


--PB1_ram_rom_data_reg[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
--operation mode is normal

PB1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[3], PB1_ram_rom_data_reg[4], NB1_q_b[3], PB1L01, VCC, PB1L9);


--DIN[2] is DIN[2]
--operation mode is normal

DIN[2]_lut_out = ADIN[2];
DIN[2] = DFFEA(DIN[2]_lut_out, CLK, VCC, , , , );


--PB1_ram_rom_data_reg[2] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]
--operation mode is normal

PB1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[3], NB1_q_b[2], PB1L01, VCC, PB1L9);


--DIN[1] is DIN[1]
--operation mode is normal

DIN[1]_lut_out = ADIN[1];
DIN[1] = DFFEA(DIN[1]_lut_out, CLK, VCC, , , , );


--PB1_ram_rom_data_reg[1] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]
--operation mode is normal

PB1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[2], NB1_q_b[1], PB1L01, VCC, PB1L9);


--DIN[0] is DIN[0]
--operation mode is normal

DIN[0]_lut_out = ADIN[0];
DIN[0] = DFFEA(DIN[0]_lut_out, CLK, VCC, , , , );


--PB1_ram_rom_data_reg[0] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
--operation mode is normal

PB1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[0], PB1_ram_rom_data_reg[1], NB1_q_b[0], PB1L01, VCC, PB1L9);


--D1L52Q is sld_hub:sld_hub_inst|HUB_TDO~reg0
--operation mode is normal

D1L52Q = AMPP_FUNCTION(!A1L51, D1L22, D1L42, D1L61, D1L81, !KB1_state[8], D1L15);


--RB1_safe_q[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[3]
--operation mode is normal

RB1_safe_q[3] = AMPP_FUNCTION(A1L51, RB1_safe_q[3], PB1L01, !HB1_Q[3], PB1_ram_rom_load_read_data, RB1L6);


--RB1_safe_q[1] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[1]
--operation mode is arithmetic

RB1_safe_q[1] = AMPP_FUNCTION(A1L51, RB1_safe_q[1], PB1L01, !HB1_Q[3], PB1_ram_rom_load_read_data, RB1L2);

--RB1L4 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

RB1L4 = AMPP_FUNCTION(RB1_safe_q[1], RB1L2);


--RB1_safe_q[0] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[0]
--operation mode is arithmetic

RB1_safe_q[0] = AMPP_FUNCTION(A1L51, RB1_safe_q[0], PB1L01, !HB1_Q[3], PB1_ram_rom_load_read_data);

--RB1L2 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

RB1L2 = AMPP_FUNCTION(RB1_safe_q[0]);


--RB1_safe_q[2] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[2]
--operation mode is arithmetic

RB1_safe_q[2] = AMPP_FUNCTION(A1L51, RB1_safe_q[2], PB1L01, !HB1_Q[3], PB1_ram_rom_load_read_data, RB1L4);

--RB1L6 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

RB1L6 = AMPP_FUNCTION(RB1_safe_q[2], RB1L4);


--PB1_ram_rom_load_read_data is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_load_read_data
--operation mode is normal

PB1_ram_rom_load_read_data = AMPP_FUNCTION(RB1_safe_q[3], RB1_safe_q[1], RB1_safe_q[0], RB1_safe_q[2]);


--HB3_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2]
--operation mode is normal

HB3_Q[2] = AMPP_FUNCTION(A1L51, HB8_Q[2], !D1L2, D1L9);


--HB8_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
--operation mode is normal

HB8_Q[2] = AMPP_FUNCTION(A1L51, PB1_ir_loaded_address_reg[1], D1L03, HB8_Q[3], D1L33, !D1L2, KB1_state[4], D1_IRSR_ENA);


--HB5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal

HB5_Q[0] = AMPP_FUNCTION(A1L51, LB1_dffe1a[1], !D1L2, D1L1);


--HB9_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]
--operation mode is normal

HB9_Q[0] = AMPP_FUNCTION(A1L51, LB1_dffe1a[7], D1_jtag_debug_mode_usr1, D1L3);


--KB1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]
--operation mode is normal

KB1_state[1] = AMPP_FUNCTION(A1L51, KB1_state[0], KB1L81, A1L71, VCC);


--D1L2 is sld_hub:sld_hub_inst|CLEAR_SIGNAL~0
--operation mode is normal

D1L2 = AMPP_FUNCTION(HB9_Q[0], KB1_state[1]);


--KB1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal

KB1_state[5] = AMPP_FUNCTION(A1L51, A1L71, KB1_state[4], KB1_state[3], VCC);


--D1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q
--operation mode is normal

D1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L51, D1_jtag_debug_mode_usr1, KB1_state[8], VCC, D1L05);


--D1L01 is sld_hub:sld_hub_inst|GEN_SHADOW_IRF~18
--operation mode is normal

D1L01 = AMPP_FUNCTION(KB1_state[5], D1_OK_TO_UPDATE_IR_Q);


--HB7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
--operation mode is normal

HB7_Q[0] = AMPP_FUNCTION(A1L51, D1L25, VCC, D1L53);


--LB1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[2]
--operation mode is normal

LB1_dffe1a[2] = AMPP_FUNCTION(A1L51, HB8_Q[2], D1L54, HB8_Q[3], HB8_Q[1], !D1L2, D1L7);


--D1L73 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~125
--operation mode is normal

D1L73 = AMPP_FUNCTION(HB7_Q[0], LB1_dffe1a[2]);


--HB6_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

HB6_Q[0] = AMPP_FUNCTION(A1L51, altera_internal_jtag, HB8_Q[8], !D1L2, D1L53);