reserv.tan.rpt

采用高速A/D的存储示波器设计

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack ; Required Time ; Actual Time                      ; From                                                                                                                                ; To                                                                                                                            ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A   ; None          ; 6.892 ns                         ; KEY1                                                                                                                                ; DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_we_reg ;                              ; CLK                          ; 0            ;
; Worst-case tco                              ; N/A   ; None          ; 13.546 ns                        ; DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a7~porta_address_reg9 ; DOUT[4]                                                                                                                       ; CLK                          ;                              ; 0            ;
; Worst-case tpd                              ; N/A   ; None          ; 5.226 ns                         ; CLK                                                                                                                                 ; DA_CLK                                                                                                                        ;                              ;                              ; 0            ;
; Worst-case th                               ; N/A   ; None          ; 3.157 ns                         ; altera_internal_jtag~TMSUTAP                                                                                                        ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[11]                                                      ;                              ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case Minimum tco                      ; N/A   ; None          ; 7.830 ns                         ; lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1]                                                                              ; TRAG[1]                                                                                                                       ; CLK                          ;                              ; 0            ;
; Worst-case Minimum tpd                      ; N/A   ; None          ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                            ; altera_reserved_tdo                                                                                                           ;                              ;                              ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A   ; None          ; 114.60 MHz ( period = 8.726 ns ) ; sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[1]                                                                                         ; sld_hub:sld_hub_inst|HUB_TDO~reg0                                                                                             ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'CLK'                          ; N/A   ; None          ; 141.16 MHz ( period = 7.084 ns ) ; DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg9 ; sld_signaltap:rsv1|acq_trigger_in_reg[15]                                                                                     ; CLK                          ; CLK                          ; 0            ;
; Total number of failed paths                ;       ;               ;                                  ;                                                                                                                                     ;                                                                                                                               ;                              ;                              ; 0            ;
+---------------------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                            ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK                          ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+------------------------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                                                                 ; To                                                                                                                                                                                                           ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 141.16 MHz ( period = 7.084 ns )                    ; DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg0                                                                                                                  ; sld_signaltap:rsv1|acq_trigger_in_reg[15]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 141.16 MHz ( period = 7.084 ns )                    ; DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg1                                                                                                                  ; sld_signaltap:rsv1|acq_trigger_in_reg[15]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 141.16 MHz ( period = 7.084 ns )                    ; DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg2                                                                                                                  ; sld_signaltap:rsv1|acq_trigger_in_reg[15]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 141.16 MHz ( period = 7.084 ns )                    ; DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg3                                                                                                                  ; sld_signaltap:rsv1|acq_trigger_in_reg[15]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 141.16 MHz ( period = 7.084 ns )                    ; DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg4                                                                                                                  ; sld_signaltap:rsv1|acq_trigger_in_reg[15]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;
; N/A                                     ; 141.16 MHz ( period = 7.084 ns )                    ; DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|ram_block3a6~porta_address_reg5                                                                                                                  ; sld_signaltap:rsv1|acq_trigger_in_reg[15]                                                                                                                                                                    ; CLK        ; CLK      ; None                        ; None                      ; None                    ;