reserv.fit.eqn

采用高速A/D的存储示波器设计

NB1_q_b[6]_PORT_B_data_out = MEMORY(NB1_q_b[6]_PORT_A_data_in_reg, NB1_q_b[6]_PORT_B_data_in_reg, NB1_q_b[6]_PORT_A_address_reg, NB1_q_b[6]_PORT_B_address_reg, NB1_q_b[6]_PORT_A_write_enable_reg, NB1_q_b[6]_PORT_B_write_enable_reg, , , NB1_q_b[6]_clock_0, NB1_q_b[6]_clock_1, , , , );
NB1_q_b[5] = NB1_q_b[6]_PORT_B_data_out[1];


--A1L61 is altera_internal_jtag~TDO at JTAG_X1_Y10_N1
A1L61 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L52Q);

--A1L71 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y10_N1
A1L71 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L52Q);

--A1L51 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y10_N1
A1L51 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L52Q);

--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y10_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !D1L52Q);


--HB1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X15_Y6_N4
--operation mode is normal

HB1_Q[2] = AMPP_FUNCTION(A1L51, HB5_Q[0], HB8_Q[2], HB3_Q[2], !D1L2, D1L83);


--PB1L33 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~1 at LC_X15_Y6_N0
--operation mode is normal

PB1L33 = AMPP_FUNCTION(HB1_Q[2]);

--PB1_ram_rom_incr_write_addr_reg is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_write_addr_reg at LC_X15_Y6_N0
--operation mode is normal

PB1_ram_rom_incr_write_addr_reg = AMPP_FUNCTION(A1L51, PB1_ram_rom_load_read_data, VCC, GND);


--PB1_ram_rom_data_reg[7] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] at LC_X19_Y6_N5
--operation mode is normal

PB1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[7], altera_internal_jtag, NB1_q_b[7], PB1L01, VCC, PB1L9);


--QB1_safe_q[0] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[0] at LC_X13_Y8_N0
--operation mode is arithmetic

QB1_safe_q[0] = AMPP_FUNCTION(A1L51, QB1_safe_q[0], PB1L31, !HB1_Q[0], PB1_ram_rom_incr_addr);

--QB1L22 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[0]~COUT0 at LC_X13_Y8_N0
--operation mode is arithmetic

QB1L22 = AMPP_FUNCTION(QB1_safe_q[0]);

--QB1L32 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[0]~COUT1 at LC_X13_Y8_N0
--operation mode is arithmetic

QB1L32 = AMPP_FUNCTION(QB1_safe_q[0]);


--QB1_safe_q[1] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[1] at LC_X13_Y8_N1
--operation mode is arithmetic

QB1_safe_q[1] = AMPP_FUNCTION(A1L51, QB1_safe_q[1], PB1L41, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L22, QB1L32);

--QB1L52 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[1]~COUT0 at LC_X13_Y8_N1
--operation mode is arithmetic

QB1L52 = AMPP_FUNCTION(QB1_safe_q[1], QB1L22);

--QB1L62 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[1]~COUT1 at LC_X13_Y8_N1
--operation mode is arithmetic

QB1L62 = AMPP_FUNCTION(QB1_safe_q[1], QB1L32);


--QB1_safe_q[2] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[2] at LC_X13_Y8_N2
--operation mode is arithmetic

QB1_safe_q[2] = AMPP_FUNCTION(A1L51, QB1_safe_q[2], PB1L51, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L52, QB1L62);

--QB1L82 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[2]~COUT0 at LC_X13_Y8_N2
--operation mode is arithmetic

QB1L82 = AMPP_FUNCTION(QB1_safe_q[2], QB1L52);

--QB1L92 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[2]~COUT1 at LC_X13_Y8_N2
--operation mode is arithmetic

QB1L92 = AMPP_FUNCTION(QB1_safe_q[2], QB1L62);


--QB1_safe_q[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[3] at LC_X13_Y8_N3
--operation mode is arithmetic

QB1_safe_q[3] = AMPP_FUNCTION(A1L51, QB1_safe_q[3], PB1L61, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L82, QB1L92);

--QB1L13 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[3]~COUT0 at LC_X13_Y8_N3
--operation mode is arithmetic

QB1L13 = AMPP_FUNCTION(QB1_safe_q[3], QB1L82);

--QB1L23 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[3]~COUT1 at LC_X13_Y8_N3
--operation mode is arithmetic

QB1L23 = AMPP_FUNCTION(QB1_safe_q[3], QB1L92);


--QB1_safe_q[4] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[4] at LC_X13_Y8_N4
--operation mode is arithmetic

QB1_safe_q[4] = AMPP_FUNCTION(A1L51, QB1_safe_q[4], PB1L71, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L13, QB1L23);

--QB1L01 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella4~COUT at LC_X13_Y8_N4
--operation mode is arithmetic

QB1L01 = AMPP_FUNCTION(QB1_safe_q[4], QB1L13, QB1L23);


--QB1_safe_q[5] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[5] at LC_X13_Y8_N5
--operation mode is arithmetic

QB1_safe_q[5] = AMPP_FUNCTION(A1L51, QB1_safe_q[5], PB1L81, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L01);

--QB1L53 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[5]~COUT0 at LC_X13_Y8_N5
--operation mode is arithmetic

QB1L53 = AMPP_FUNCTION(QB1_safe_q[5]);

--QB1L63 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[5]~COUT1 at LC_X13_Y8_N5
--operation mode is arithmetic

QB1L63 = AMPP_FUNCTION(QB1_safe_q[5]);


--QB1_safe_q[6] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[6] at LC_X13_Y8_N6
--operation mode is arithmetic

QB1_safe_q[6] = AMPP_FUNCTION(A1L51, QB1_safe_q[6], PB1L91, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L01, QB1L53, QB1L63);

--QB1L83 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[6]~COUT0 at LC_X13_Y8_N6
--operation mode is arithmetic

QB1L83 = AMPP_FUNCTION(QB1_safe_q[6], QB1L53);

--QB1L93 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[6]~COUT1 at LC_X13_Y8_N6
--operation mode is arithmetic

QB1L93 = AMPP_FUNCTION(QB1_safe_q[6], QB1L63);


--QB1_safe_q[7] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[7] at LC_X13_Y8_N7
--operation mode is arithmetic

QB1_safe_q[7] = AMPP_FUNCTION(A1L51, QB1_safe_q[7], PB1L02, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L01, QB1L83, QB1L93);

--QB1L14 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[7]~COUT0 at LC_X13_Y8_N7
--operation mode is arithmetic

QB1L14 = AMPP_FUNCTION(QB1_safe_q[7], QB1L83);

--QB1L24 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[7]~COUT1 at LC_X13_Y8_N7
--operation mode is arithmetic

QB1L24 = AMPP_FUNCTION(QB1_safe_q[7], QB1L93);


--QB1_safe_q[8] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[8] at LC_X13_Y8_N8
--operation mode is arithmetic

QB1_safe_q[8] = AMPP_FUNCTION(A1L51, QB1_safe_q[8], PB1L12, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L01, QB1L14, QB1L24);

--QB1L44 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[8]~COUT0 at LC_X13_Y8_N8
--operation mode is arithmetic

QB1L44 = AMPP_FUNCTION(QB1_safe_q[8], QB1L14);

--QB1L54 is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[8]~COUT1 at LC_X13_Y8_N8
--operation mode is arithmetic

QB1L54 = AMPP_FUNCTION(QB1_safe_q[8], QB1L24);


--QB1_safe_q[9] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[9] at LC_X13_Y8_N9
--operation mode is normal

QB1_safe_q[9] = AMPP_FUNCTION(A1L51, QB1_safe_q[9], PB1L22, !HB1_Q[0], PB1_ram_rom_incr_addr, QB1L01, QB1L44, QB1L54);


--PB1_ram_rom_data_reg[6] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] at LC_X19_Y6_N2
--operation mode is normal

PB1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[7], NB1_q_b[6], PB1L01, VCC, PB1L9);


--PB1_ram_rom_data_reg[5] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] at LC_X19_Y6_N4
--operation mode is normal

PB1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], NB1_q_b[5], PB1L01, VCC, PB1L9);


--PB1_ram_rom_data_reg[4] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] at LC_X16_Y10_N5
--operation mode is normal

PB1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[5], PB1L01, NB1_q_b[4], PB1_ram_rom_data_reg[4], VCC, PB1L9);


--PB1_ram_rom_data_reg[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] at LC_X16_Y10_N6
--operation mode is normal

PB1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[3], PB1_ram_rom_data_reg[4], NB1_q_b[3], PB1L01, VCC, PB1L9);


--PB1_ram_rom_data_reg[2] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] at LC_X16_Y10_N8
--operation mode is normal

PB1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[2], PB1L01, NB1_q_b[2], PB1_ram_rom_data_reg[3], VCC, PB1L9);


--PB1_ram_rom_data_reg[1] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] at LC_X16_Y10_N2
--operation mode is normal

PB1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[1], PB1L01, NB1_q_b[1], PB1_ram_rom_data_reg[2], VCC, PB1L9);


--PB1_ram_rom_data_reg[0] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] at LC_X16_Y10_N4
--operation mode is normal

PB1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L51, PB1_ram_rom_data_reg[1], PB1L01, NB1_q_b[0], PB1_ram_rom_data_reg[0], VCC, PB1L9);


--D1L52Q is sld_hub:sld_hub_inst|HUB_TDO~reg0 at LC_X16_Y7_N1
--operation mode is normal

D1L52Q = AMPP_FUNCTION(!A1L51, D1L42, D1L61, D1L81, D1L22, !KB1_state[8], D1L15);


--RB1_safe_q[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[3] at LC_X14_Y9_N4
--operation mode is normal