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📄 reserv.fit.eqn

📁 采用高速A/D的存储示波器设计
💻 EQN
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NB1_q_a[7]_PORT_A_data_in = BUS(DIN[7], DIN[2], DIN[1], DIN[0]);
NB1_q_a[7]_PORT_A_data_in_reg = DFFE(NB1_q_a[7]_PORT_A_data_in, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_a[7]_PORT_B_data_in_reg = DFFE(NB1_q_a[7]_PORT_B_data_in, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[7]_PORT_A_address_reg = DFFE(NB1_q_a[7]_PORT_A_address, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[7]_PORT_B_address_reg = DFFE(NB1_q_a[7]_PORT_B_address, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_write_enable = KEY1;
NB1_q_a[7]_PORT_A_write_enable_reg = DFFE(NB1_q_a[7]_PORT_A_write_enable, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_write_enable = PB1L33;
NB1_q_a[7]_PORT_B_write_enable_reg = DFFE(NB1_q_a[7]_PORT_B_write_enable, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_clock_0 = GLOBAL(CLK);
NB1_q_a[7]_clock_1 = GLOBAL(A1L51);
NB1_q_a[7]_PORT_A_data_out = MEMORY(NB1_q_a[7]_PORT_A_data_in_reg, NB1_q_a[7]_PORT_B_data_in_reg, NB1_q_a[7]_PORT_A_address_reg, NB1_q_a[7]_PORT_B_address_reg, NB1_q_a[7]_PORT_A_write_enable_reg, NB1_q_a[7]_PORT_B_write_enable_reg, , , NB1_q_a[7]_clock_0, NB1_q_a[7]_clock_1, , , , );
NB1_q_a[1] = NB1_q_a[7]_PORT_A_data_out[2];

--NB1_q_a[2] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[2] at M4K_X17_Y10
NB1_q_a[7]_PORT_A_data_in = BUS(DIN[7], DIN[2], DIN[1], DIN[0]);
NB1_q_a[7]_PORT_A_data_in_reg = DFFE(NB1_q_a[7]_PORT_A_data_in, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_a[7]_PORT_B_data_in_reg = DFFE(NB1_q_a[7]_PORT_B_data_in, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[7]_PORT_A_address_reg = DFFE(NB1_q_a[7]_PORT_A_address, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[7]_PORT_B_address_reg = DFFE(NB1_q_a[7]_PORT_B_address, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_write_enable = KEY1;
NB1_q_a[7]_PORT_A_write_enable_reg = DFFE(NB1_q_a[7]_PORT_A_write_enable, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_write_enable = PB1L33;
NB1_q_a[7]_PORT_B_write_enable_reg = DFFE(NB1_q_a[7]_PORT_B_write_enable, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_clock_0 = GLOBAL(CLK);
NB1_q_a[7]_clock_1 = GLOBAL(A1L51);
NB1_q_a[7]_PORT_A_data_out = MEMORY(NB1_q_a[7]_PORT_A_data_in_reg, NB1_q_a[7]_PORT_B_data_in_reg, NB1_q_a[7]_PORT_A_address_reg, NB1_q_a[7]_PORT_B_address_reg, NB1_q_a[7]_PORT_A_write_enable_reg, NB1_q_a[7]_PORT_B_write_enable_reg, , , NB1_q_a[7]_clock_0, NB1_q_a[7]_clock_1, , , , );
NB1_q_a[2] = NB1_q_a[7]_PORT_A_data_out[1];

--NB1_q_b[0] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[0] at M4K_X17_Y10
NB1_q_b[7]_PORT_A_data_in = BUS(DIN[7], DIN[2], DIN[1], DIN[0]);
NB1_q_b[7]_PORT_A_data_in_reg = DFFE(NB1_q_b[7]_PORT_A_data_in, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_b[7]_PORT_B_data_in_reg = DFFE(NB1_q_b[7]_PORT_B_data_in, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[7]_PORT_A_address_reg = DFFE(NB1_q_b[7]_PORT_A_address, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[7]_PORT_B_address_reg = DFFE(NB1_q_b[7]_PORT_B_address, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_write_enable = KEY1;
NB1_q_b[7]_PORT_A_write_enable_reg = DFFE(NB1_q_b[7]_PORT_A_write_enable, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_write_enable = PB1L33;
NB1_q_b[7]_PORT_B_write_enable_reg = DFFE(NB1_q_b[7]_PORT_B_write_enable, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_clock_0 = GLOBAL(CLK);
NB1_q_b[7]_clock_1 = GLOBAL(A1L51);
NB1_q_b[7]_PORT_B_data_out = MEMORY(NB1_q_b[7]_PORT_A_data_in_reg, NB1_q_b[7]_PORT_B_data_in_reg, NB1_q_b[7]_PORT_A_address_reg, NB1_q_b[7]_PORT_B_address_reg, NB1_q_b[7]_PORT_A_write_enable_reg, NB1_q_b[7]_PORT_B_write_enable_reg, , , NB1_q_b[7]_clock_0, NB1_q_b[7]_clock_1, , , , );
NB1_q_b[0] = NB1_q_b[7]_PORT_B_data_out[3];

--NB1_q_b[1] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[1] at M4K_X17_Y10
NB1_q_b[7]_PORT_A_data_in = BUS(DIN[7], DIN[2], DIN[1], DIN[0]);
NB1_q_b[7]_PORT_A_data_in_reg = DFFE(NB1_q_b[7]_PORT_A_data_in, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_b[7]_PORT_B_data_in_reg = DFFE(NB1_q_b[7]_PORT_B_data_in, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[7]_PORT_A_address_reg = DFFE(NB1_q_b[7]_PORT_A_address, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[7]_PORT_B_address_reg = DFFE(NB1_q_b[7]_PORT_B_address, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_write_enable = KEY1;
NB1_q_b[7]_PORT_A_write_enable_reg = DFFE(NB1_q_b[7]_PORT_A_write_enable, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_write_enable = PB1L33;
NB1_q_b[7]_PORT_B_write_enable_reg = DFFE(NB1_q_b[7]_PORT_B_write_enable, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_clock_0 = GLOBAL(CLK);
NB1_q_b[7]_clock_1 = GLOBAL(A1L51);
NB1_q_b[7]_PORT_B_data_out = MEMORY(NB1_q_b[7]_PORT_A_data_in_reg, NB1_q_b[7]_PORT_B_data_in_reg, NB1_q_b[7]_PORT_A_address_reg, NB1_q_b[7]_PORT_B_address_reg, NB1_q_b[7]_PORT_A_write_enable_reg, NB1_q_b[7]_PORT_B_write_enable_reg, , , NB1_q_b[7]_clock_0, NB1_q_b[7]_clock_1, , , , );
NB1_q_b[1] = NB1_q_b[7]_PORT_B_data_out[2];

--NB1_q_b[2] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[2] at M4K_X17_Y10
NB1_q_b[7]_PORT_A_data_in = BUS(DIN[7], DIN[2], DIN[1], DIN[0]);
NB1_q_b[7]_PORT_A_data_in_reg = DFFE(NB1_q_b[7]_PORT_A_data_in, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_b[7]_PORT_B_data_in_reg = DFFE(NB1_q_b[7]_PORT_B_data_in, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[7]_PORT_A_address_reg = DFFE(NB1_q_b[7]_PORT_A_address, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[7]_PORT_B_address_reg = DFFE(NB1_q_b[7]_PORT_B_address, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_write_enable = KEY1;
NB1_q_b[7]_PORT_A_write_enable_reg = DFFE(NB1_q_b[7]_PORT_A_write_enable, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_write_enable = PB1L33;
NB1_q_b[7]_PORT_B_write_enable_reg = DFFE(NB1_q_b[7]_PORT_B_write_enable, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_clock_0 = GLOBAL(CLK);
NB1_q_b[7]_clock_1 = GLOBAL(A1L51);
NB1_q_b[7]_PORT_B_data_out = MEMORY(NB1_q_b[7]_PORT_A_data_in_reg, NB1_q_b[7]_PORT_B_data_in_reg, NB1_q_b[7]_PORT_A_address_reg, NB1_q_b[7]_PORT_B_address_reg, NB1_q_b[7]_PORT_A_write_enable_reg, NB1_q_b[7]_PORT_B_write_enable_reg, , , NB1_q_b[7]_clock_0, NB1_q_b[7]_clock_1, , , , );
NB1_q_b[2] = NB1_q_b[7]_PORT_B_data_out[1];


--NB1_q_a[6] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[6] at M4K_X17_Y6
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[6]_PORT_A_data_in = BUS(DIN[6], DIN[5], DIN[4], DIN[3]);
NB1_q_a[6]_PORT_A_data_in_reg = DFFE(NB1_q_a[6]_PORT_A_data_in, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3]);
NB1_q_a[6]_PORT_B_data_in_reg = DFFE(NB1_q_a[6]_PORT_B_data_in, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[6]_PORT_A_address_reg = DFFE(NB1_q_a[6]_PORT_A_address, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[6]_PORT_B_address_reg = DFFE(NB1_q_a[6]_PORT_B_address, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_write_enable = KEY1;
NB1_q_a[6]_PORT_A_write_enable_reg = DFFE(NB1_q_a[6]_PORT_A_write_enable, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_write_enable = PB1L33;
NB1_q_a[6]_PORT_B_write_enable_reg = DFFE(NB1_q_a[6]_PORT_B_write_enable, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_clock_0 = GLOBAL(CLK);
NB1_q_a[6]_clock_1 = GLOBAL(A1L51);
NB1_q_a[6]_PORT_A_data_out = MEMORY(NB1_q_a[6]_PORT_A_data_in_reg, NB1_q_a[6]_PORT_B_data_in_reg, NB1_q_a[6]_PORT_A_address_reg, NB1_q_a[6]_PORT_B_address_reg, NB1_q_a[6]_PORT_A_write_enable_reg, NB1_q_a[6]_PORT_B_write_enable_reg, , , NB1_q_a[6]_clock_0, NB1_q_a[6]_clock_1, , , , );
NB1_q_a[6] = NB1_q_a[6]_PORT_A_data_out[0];

--NB1_q_b[6] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[6] at M4K_X17_Y6
NB1_q_b[6]_PORT_A_data_in = BUS(DIN[6], DIN[5], DIN[4], DIN[3]);
NB1_q_b[6]_PORT_A_data_in_reg = DFFE(NB1_q_b[6]_PORT_A_data_in, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3]);
NB1_q_b[6]_PORT_B_data_in_reg = DFFE(NB1_q_b[6]_PORT_B_data_in, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[6]_PORT_A_address_reg = DFFE(NB1_q_b[6]_PORT_A_address, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[6]_PORT_B_address_reg = DFFE(NB1_q_b[6]_PORT_B_address, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_write_enable = KEY1;
NB1_q_b[6]_PORT_A_write_enable_reg = DFFE(NB1_q_b[6]_PORT_A_write_enable, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_write_enable = PB1L33;
NB1_q_b[6]_PORT_B_write_enable_reg = DFFE(NB1_q_b[6]_PORT_B_write_enable, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_clock_0 = GLOBAL(CLK);
NB1_q_b[6]_clock_1 = GLOBAL(A1L51);
NB1_q_b[6]_PORT_B_data_out = MEMORY(NB1_q_b[6]_PORT_A_data_in_reg, NB1_q_b[6]_PORT_B_data_in_reg, NB1_q_b[6]_PORT_A_address_reg, NB1_q_b[6]_PORT_B_address_reg, NB1_q_b[6]_PORT_A_write_enable_reg, NB1_q_b[6]_PORT_B_write_enable_reg, , , NB1_q_b[6]_clock_0, NB1_q_b[6]_clock_1, , , , );
NB1_q_b[6] = NB1_q_b[6]_PORT_B_data_out[0];

--NB1_q_a[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[3] at M4K_X17_Y6
NB1_q_a[6]_PORT_A_data_in = BUS(DIN[6], DIN[5], DIN[4], DIN[3]);
NB1_q_a[6]_PORT_A_data_in_reg = DFFE(NB1_q_a[6]_PORT_A_data_in, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3]);
NB1_q_a[6]_PORT_B_data_in_reg = DFFE(NB1_q_a[6]_PORT_B_data_in, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[6]_PORT_A_address_reg = DFFE(NB1_q_a[6]_PORT_A_address, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[6]_PORT_B_address_reg = DFFE(NB1_q_a[6]_PORT_B_address, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_write_enable = KEY1;
NB1_q_a[6]_PORT_A_write_enable_reg = DFFE(NB1_q_a[6]_PORT_A_write_enable, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_write_enable = PB1L33;
NB1_q_a[6]_PORT_B_write_enable_reg = DFFE(NB1_q_a[6]_PORT_B_write_enable, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_clock_0 = GLOBAL(CLK);
NB1_q_a[6]_clock_1 = GLOBAL(A1L51);
NB1_q_a[6]_PORT_A_data_out = MEMORY(NB1_q_a[6]_PORT_A_data_in_reg, NB1_q_a[6]_PORT_B_data_in_reg, NB1_q_a[6]_PORT_A_address_reg, NB1_q_a[6]_PORT_B_address_reg, NB1_q_a[6]_PORT_A_write_enable_reg, NB1_q_a[6]_PORT_B_write_enable_reg, , , NB1_q_a[6]_clock_0, NB1_q_a[6]_clock_1, , , , );
NB1_q_a[3] = NB1_q_a[6]_PORT_A_data_out[3];

--NB1_q_a[4] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[4] at M4K_X17_Y6
NB1_q_a[6]_PORT_A_data_in = BUS(DIN[6], DIN[5], DIN[4], DIN[3]);
NB1_q_a[6]_PORT_A_data_in_reg = DFFE(NB1_q_a[6]_PORT_A_data_in, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3]);
NB1_q_a[6]_PORT_B_data_in_reg = DFFE(NB1_q_a[6]_PORT_B_data_in, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[6]_PORT_A_address_reg = DFFE(NB1_q_a[6]_PORT_A_address, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[6]_PORT_B_address_reg = DFFE(NB1_q_a[6]_PORT_B_address, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_write_enable = KEY1;
NB1_q_a[6]_PORT_A_write_enable_reg = DFFE(NB1_q_a[6]_PORT_A_write_enable, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_write_enable = PB1L33;
NB1_q_a[6]_PORT_B_write_enable_reg = DFFE(NB1_q_a[6]_PORT_B_write_enable, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_clock_0 = GLOBAL(CLK);
NB1_q_a[6]_clock_1 = GLOBAL(A1L51);
NB1_q_a[6]_PORT_A_data_out = MEMORY(NB1_q_a[6]_PORT_A_data_in_reg, NB1_q_a[6]_PORT_B_data_in_reg, NB1_q_a[6]_PORT_A_address_reg, NB1_q_a[6]_PORT_B_address_reg, NB1_q_a[6]_PORT_A_write_enable_reg, NB1_q_a[6]_PORT_B_write_enable_reg, , , NB1_q_a[6]_clock_0, NB1_q_a[6]_clock_1, , , , );
NB1_q_a[4] = NB1_q_a[6]_PORT_A_data_out[2];

--NB1_q_a[5] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[5] at M4K_X17_Y6
NB1_q_a[6]_PORT_A_data_in = BUS(DIN[6], DIN[5], DIN[4], DIN[3]);
NB1_q_a[6]_PORT_A_data_in_reg = DFFE(NB1_q_a[6]_PORT_A_data_in, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3]);
NB1_q_a[6]_PORT_B_data_in_reg = DFFE(NB1_q_a[6]_PORT_B_data_in, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[6]_PORT_A_address_reg = DFFE(NB1_q_a[6]_PORT_A_address, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[6]_PORT_B_address_reg = DFFE(NB1_q_a[6]_PORT_B_address, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_PORT_A_write_enable = KEY1;
NB1_q_a[6]_PORT_A_write_enable_reg = DFFE(NB1_q_a[6]_PORT_A_write_enable, NB1_q_a[6]_clock_0, , , );
NB1_q_a[6]_PORT_B_write_enable = PB1L33;
NB1_q_a[6]_PORT_B_write_enable_reg = DFFE(NB1_q_a[6]_PORT_B_write_enable, NB1_q_a[6]_clock_1, , , );
NB1_q_a[6]_clock_0 = GLOBAL(CLK);
NB1_q_a[6]_clock_1 = GLOBAL(A1L51);
NB1_q_a[6]_PORT_A_data_out = MEMORY(NB1_q_a[6]_PORT_A_data_in_reg, NB1_q_a[6]_PORT_B_data_in_reg, NB1_q_a[6]_PORT_A_address_reg, NB1_q_a[6]_PORT_B_address_reg, NB1_q_a[6]_PORT_A_write_enable_reg, NB1_q_a[6]_PORT_B_write_enable_reg, , , NB1_q_a[6]_clock_0, NB1_q_a[6]_clock_1, , , , );
NB1_q_a[5] = NB1_q_a[6]_PORT_A_data_out[1];

--NB1_q_b[3] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[3] at M4K_X17_Y6
NB1_q_b[6]_PORT_A_data_in = BUS(DIN[6], DIN[5], DIN[4], DIN[3]);
NB1_q_b[6]_PORT_A_data_in_reg = DFFE(NB1_q_b[6]_PORT_A_data_in, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3]);
NB1_q_b[6]_PORT_B_data_in_reg = DFFE(NB1_q_b[6]_PORT_B_data_in, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[6]_PORT_A_address_reg = DFFE(NB1_q_b[6]_PORT_A_address, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[6]_PORT_B_address_reg = DFFE(NB1_q_b[6]_PORT_B_address, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_write_enable = KEY1;
NB1_q_b[6]_PORT_A_write_enable_reg = DFFE(NB1_q_b[6]_PORT_A_write_enable, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_write_enable = PB1L33;
NB1_q_b[6]_PORT_B_write_enable_reg = DFFE(NB1_q_b[6]_PORT_B_write_enable, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_clock_0 = GLOBAL(CLK);
NB1_q_b[6]_clock_1 = GLOBAL(A1L51);
NB1_q_b[6]_PORT_B_data_out = MEMORY(NB1_q_b[6]_PORT_A_data_in_reg, NB1_q_b[6]_PORT_B_data_in_reg, NB1_q_b[6]_PORT_A_address_reg, NB1_q_b[6]_PORT_B_address_reg, NB1_q_b[6]_PORT_A_write_enable_reg, NB1_q_b[6]_PORT_B_write_enable_reg, , , NB1_q_b[6]_clock_0, NB1_q_b[6]_clock_1, , , , );
NB1_q_b[3] = NB1_q_b[6]_PORT_B_data_out[3];

--NB1_q_b[4] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[4] at M4K_X17_Y6
NB1_q_b[6]_PORT_A_data_in = BUS(DIN[6], DIN[5], DIN[4], DIN[3]);
NB1_q_b[6]_PORT_A_data_in_reg = DFFE(NB1_q_b[6]_PORT_A_data_in, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3]);
NB1_q_b[6]_PORT_B_data_in_reg = DFFE(NB1_q_b[6]_PORT_B_data_in, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[6]_PORT_A_address_reg = DFFE(NB1_q_b[6]_PORT_A_address, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[6]_PORT_B_address_reg = DFFE(NB1_q_b[6]_PORT_B_address, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_write_enable = KEY1;
NB1_q_b[6]_PORT_A_write_enable_reg = DFFE(NB1_q_b[6]_PORT_A_write_enable, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_write_enable = PB1L33;
NB1_q_b[6]_PORT_B_write_enable_reg = DFFE(NB1_q_b[6]_PORT_B_write_enable, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_clock_0 = GLOBAL(CLK);
NB1_q_b[6]_clock_1 = GLOBAL(A1L51);
NB1_q_b[6]_PORT_B_data_out = MEMORY(NB1_q_b[6]_PORT_A_data_in_reg, NB1_q_b[6]_PORT_B_data_in_reg, NB1_q_b[6]_PORT_A_address_reg, NB1_q_b[6]_PORT_B_address_reg, NB1_q_b[6]_PORT_A_write_enable_reg, NB1_q_b[6]_PORT_B_write_enable_reg, , , NB1_q_b[6]_clock_0, NB1_q_b[6]_clock_1, , , , );
NB1_q_b[4] = NB1_q_b[6]_PORT_B_data_out[2];

--NB1_q_b[5] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[5] at M4K_X17_Y6
NB1_q_b[6]_PORT_A_data_in = BUS(DIN[6], DIN[5], DIN[4], DIN[3]);
NB1_q_b[6]_PORT_A_data_in_reg = DFFE(NB1_q_b[6]_PORT_A_data_in, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[6], PB1_ram_rom_data_reg[5], PB1_ram_rom_data_reg[4], PB1_ram_rom_data_reg[3]);
NB1_q_b[6]_PORT_B_data_in_reg = DFFE(NB1_q_b[6]_PORT_B_data_in, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[6]_PORT_A_address_reg = DFFE(NB1_q_b[6]_PORT_A_address, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[6]_PORT_B_address_reg = DFFE(NB1_q_b[6]_PORT_B_address, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_PORT_A_write_enable = KEY1;
NB1_q_b[6]_PORT_A_write_enable_reg = DFFE(NB1_q_b[6]_PORT_A_write_enable, NB1_q_b[6]_clock_0, , , );
NB1_q_b[6]_PORT_B_write_enable = PB1L33;
NB1_q_b[6]_PORT_B_write_enable_reg = DFFE(NB1_q_b[6]_PORT_B_write_enable, NB1_q_b[6]_clock_1, , , );
NB1_q_b[6]_clock_0 = GLOBAL(CLK);
NB1_q_b[6]_clock_1 = GLOBAL(A1L51);
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