reserv.fit.eqn

采用高速A/D的存储示波器设计

--F1_safe_q[9] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[9] at LC_X23_Y10_N9
--operation mode is normal

F1_safe_q[9]_carry_eqn = (!F1L01 & F1L44) # (F1L01 & F1L54);
F1_safe_q[9]_lut_out = F1_safe_q[9] $ F1_safe_q[9]_carry_eqn;
F1_safe_q[9] = DFFEA(F1_safe_q[9]_lut_out, GLOBAL(CLK), VCC, , , , );


--F1_safe_q[8] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[8] at LC_X23_Y10_N8
--operation mode is arithmetic

F1_safe_q[8]_carry_eqn = (!F1L01 & F1L14) # (F1L01 & F1L24);
F1_safe_q[8]_lut_out = F1_safe_q[8] $ !F1_safe_q[8]_carry_eqn;
F1_safe_q[8] = DFFEA(F1_safe_q[8]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L44 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[8]~COUT0 at LC_X23_Y10_N8
--operation mode is arithmetic

F1L44_cout_0 = F1_safe_q[8] & !F1L14;
F1L44 = CARRY(F1L44_cout_0);

--F1L54 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[8]~COUT1 at LC_X23_Y10_N8
--operation mode is arithmetic

F1L54_cout_1 = F1_safe_q[8] & !F1L24;
F1L54 = CARRY(F1L54_cout_1);


--F1_safe_q[7] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[7] at LC_X23_Y10_N7
--operation mode is arithmetic

F1_safe_q[7]_carry_eqn = (!F1L01 & F1L83) # (F1L01 & F1L93);
F1_safe_q[7]_lut_out = F1_safe_q[7] $ F1_safe_q[7]_carry_eqn;
F1_safe_q[7] = DFFEA(F1_safe_q[7]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L14 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[7]~COUT0 at LC_X23_Y10_N7
--operation mode is arithmetic

F1L14_cout_0 = !F1L83 # !F1_safe_q[7];
F1L14 = CARRY(F1L14_cout_0);

--F1L24 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[7]~COUT1 at LC_X23_Y10_N7
--operation mode is arithmetic

F1L24_cout_1 = !F1L93 # !F1_safe_q[7];
F1L24 = CARRY(F1L24_cout_1);


--F1_safe_q[6] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[6] at LC_X23_Y10_N6
--operation mode is arithmetic

F1_safe_q[6]_carry_eqn = (!F1L01 & F1L53) # (F1L01 & F1L63);
F1_safe_q[6]_lut_out = F1_safe_q[6] $ !F1_safe_q[6]_carry_eqn;
F1_safe_q[6] = DFFEA(F1_safe_q[6]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L83 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[6]~COUT0 at LC_X23_Y10_N6
--operation mode is arithmetic

F1L83_cout_0 = F1_safe_q[6] & !F1L53;
F1L83 = CARRY(F1L83_cout_0);

--F1L93 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[6]~COUT1 at LC_X23_Y10_N6
--operation mode is arithmetic

F1L93_cout_1 = F1_safe_q[6] & !F1L63;
F1L93 = CARRY(F1L93_cout_1);


--F1_safe_q[5] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[5] at LC_X23_Y10_N5
--operation mode is arithmetic

F1_safe_q[5]_carry_eqn = F1L01;
F1_safe_q[5]_lut_out = F1_safe_q[5] $ F1_safe_q[5]_carry_eqn;
F1_safe_q[5] = DFFEA(F1_safe_q[5]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L53 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[5]~COUT0 at LC_X23_Y10_N5
--operation mode is arithmetic

F1L53_cout_0 = !F1L01 # !F1_safe_q[5];
F1L53 = CARRY(F1L53_cout_0);

--F1L63 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[5]~COUT1 at LC_X23_Y10_N5
--operation mode is arithmetic

F1L63_cout_1 = !F1L01 # !F1_safe_q[5];
F1L63 = CARRY(F1L63_cout_1);


--F1_safe_q[4] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[4] at LC_X23_Y10_N4
--operation mode is arithmetic

F1_safe_q[4]_lut_out = F1_safe_q[4] $ !F1L13;
F1_safe_q[4] = DFFEA(F1_safe_q[4]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L01 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|counter_cella4~COUT at LC_X23_Y10_N4
--operation mode is arithmetic

F1L01 = CARRY(F1_safe_q[4] & !F1L23);


--F1_safe_q[3] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[3] at LC_X23_Y10_N3
--operation mode is arithmetic

F1_safe_q[3]_lut_out = F1_safe_q[3] $ F1L82;
F1_safe_q[3] = DFFEA(F1_safe_q[3]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L13 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[3]~COUT0 at LC_X23_Y10_N3
--operation mode is arithmetic

F1L13_cout_0 = !F1L82 # !F1_safe_q[3];
F1L13 = CARRY(F1L13_cout_0);

--F1L23 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[3]~COUT1 at LC_X23_Y10_N3
--operation mode is arithmetic

F1L23_cout_1 = !F1L92 # !F1_safe_q[3];
F1L23 = CARRY(F1L23_cout_1);


--F1_safe_q[2] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[2] at LC_X23_Y10_N2
--operation mode is arithmetic

F1_safe_q[2]_lut_out = F1_safe_q[2] $ !F1L52;
F1_safe_q[2] = DFFEA(F1_safe_q[2]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L82 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[2]~COUT0 at LC_X23_Y10_N2
--operation mode is arithmetic

F1L82_cout_0 = F1_safe_q[2] & !F1L52;
F1L82 = CARRY(F1L82_cout_0);

--F1L92 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[2]~COUT1 at LC_X23_Y10_N2
--operation mode is arithmetic

F1L92_cout_1 = F1_safe_q[2] & !F1L62;
F1L92 = CARRY(F1L92_cout_1);


--F1_safe_q[1] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1] at LC_X23_Y10_N1
--operation mode is arithmetic

F1_safe_q[1]_lut_out = F1_safe_q[1] $ F1L22;
F1_safe_q[1] = DFFEA(F1_safe_q[1]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L52 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1]~COUT0 at LC_X23_Y10_N1
--operation mode is arithmetic

F1L52_cout_0 = !F1L22 # !F1_safe_q[1];
F1L52 = CARRY(F1L52_cout_0);

--F1L62 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[1]~COUT1 at LC_X23_Y10_N1
--operation mode is arithmetic

F1L62_cout_1 = !F1L32 # !F1_safe_q[1];
F1L62 = CARRY(F1L62_cout_1);


--F1_safe_q[0] is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[0] at LC_X23_Y10_N0
--operation mode is arithmetic

F1_safe_q[0]_lut_out = !F1_safe_q[0];
F1_safe_q[0] = DFFEA(F1_safe_q[0]_lut_out, GLOBAL(CLK), VCC, , , , );

--F1L22 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[0]~COUT0 at LC_X23_Y10_N0
--operation mode is arithmetic

F1L22_cout_0 = F1_safe_q[0];
F1L22 = CARRY(F1L22_cout_0);

--F1L32 is lpm_counter:Q1_rtl_0|cntr_pt6:auto_generated|safe_q[0]~COUT1 at LC_X23_Y10_N0
--operation mode is arithmetic

F1L32_cout_1 = F1_safe_q[0];
F1L32 = CARRY(F1L32_cout_1);


--NB1_q_a[7] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[7] at M4K_X17_Y10
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 8, Port B Logical Depth: 1024, Port B Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered, Port B Input: Registered, Port B Output: Un-registered
NB1_q_a[7]_PORT_A_data_in = BUS(DIN[7], DIN[2], DIN[1], DIN[0]);
NB1_q_a[7]_PORT_A_data_in_reg = DFFE(NB1_q_a[7]_PORT_A_data_in, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_a[7]_PORT_B_data_in_reg = DFFE(NB1_q_a[7]_PORT_B_data_in, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[7]_PORT_A_address_reg = DFFE(NB1_q_a[7]_PORT_A_address, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[7]_PORT_B_address_reg = DFFE(NB1_q_a[7]_PORT_B_address, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_write_enable = KEY1;
NB1_q_a[7]_PORT_A_write_enable_reg = DFFE(NB1_q_a[7]_PORT_A_write_enable, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_write_enable = PB1L33;
NB1_q_a[7]_PORT_B_write_enable_reg = DFFE(NB1_q_a[7]_PORT_B_write_enable, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_clock_0 = GLOBAL(CLK);
NB1_q_a[7]_clock_1 = GLOBAL(A1L51);
NB1_q_a[7]_PORT_A_data_out = MEMORY(NB1_q_a[7]_PORT_A_data_in_reg, NB1_q_a[7]_PORT_B_data_in_reg, NB1_q_a[7]_PORT_A_address_reg, NB1_q_a[7]_PORT_B_address_reg, NB1_q_a[7]_PORT_A_write_enable_reg, NB1_q_a[7]_PORT_B_write_enable_reg, , , NB1_q_a[7]_clock_0, NB1_q_a[7]_clock_1, , , , );
NB1_q_a[7] = NB1_q_a[7]_PORT_A_data_out[0];

--NB1_q_b[7] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_b[7] at M4K_X17_Y10
NB1_q_b[7]_PORT_A_data_in = BUS(DIN[7], DIN[2], DIN[1], DIN[0]);
NB1_q_b[7]_PORT_A_data_in_reg = DFFE(NB1_q_b[7]_PORT_A_data_in, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_b[7]_PORT_B_data_in_reg = DFFE(NB1_q_b[7]_PORT_B_data_in, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_b[7]_PORT_A_address_reg = DFFE(NB1_q_b[7]_PORT_A_address, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_b[7]_PORT_B_address_reg = DFFE(NB1_q_b[7]_PORT_B_address, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_PORT_A_write_enable = KEY1;
NB1_q_b[7]_PORT_A_write_enable_reg = DFFE(NB1_q_b[7]_PORT_A_write_enable, NB1_q_b[7]_clock_0, , , );
NB1_q_b[7]_PORT_B_write_enable = PB1L33;
NB1_q_b[7]_PORT_B_write_enable_reg = DFFE(NB1_q_b[7]_PORT_B_write_enable, NB1_q_b[7]_clock_1, , , );
NB1_q_b[7]_clock_0 = GLOBAL(CLK);
NB1_q_b[7]_clock_1 = GLOBAL(A1L51);
NB1_q_b[7]_PORT_B_data_out = MEMORY(NB1_q_b[7]_PORT_A_data_in_reg, NB1_q_b[7]_PORT_B_data_in_reg, NB1_q_b[7]_PORT_A_address_reg, NB1_q_b[7]_PORT_B_address_reg, NB1_q_b[7]_PORT_A_write_enable_reg, NB1_q_b[7]_PORT_B_write_enable_reg, , , NB1_q_b[7]_clock_0, NB1_q_b[7]_clock_1, , , , );
NB1_q_b[7] = NB1_q_b[7]_PORT_B_data_out[0];

--NB1_q_a[0] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[0] at M4K_X17_Y10
NB1_q_a[7]_PORT_A_data_in = BUS(DIN[7], DIN[2], DIN[1], DIN[0]);
NB1_q_a[7]_PORT_A_data_in_reg = DFFE(NB1_q_a[7]_PORT_A_data_in, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_data_in = BUS(PB1_ram_rom_data_reg[7], PB1_ram_rom_data_reg[2], PB1_ram_rom_data_reg[1], PB1_ram_rom_data_reg[0]);
NB1_q_a[7]_PORT_B_data_in_reg = DFFE(NB1_q_a[7]_PORT_B_data_in, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_address = BUS(F1_safe_q[0], F1_safe_q[1], F1_safe_q[2], F1_safe_q[3], F1_safe_q[4], F1_safe_q[5], F1_safe_q[6], F1_safe_q[7], F1_safe_q[8], F1_safe_q[9]);
NB1_q_a[7]_PORT_A_address_reg = DFFE(NB1_q_a[7]_PORT_A_address, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_address = BUS(QB1_safe_q[0], QB1_safe_q[1], QB1_safe_q[2], QB1_safe_q[3], QB1_safe_q[4], QB1_safe_q[5], QB1_safe_q[6], QB1_safe_q[7], QB1_safe_q[8], QB1_safe_q[9]);
NB1_q_a[7]_PORT_B_address_reg = DFFE(NB1_q_a[7]_PORT_B_address, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_PORT_A_write_enable = KEY1;
NB1_q_a[7]_PORT_A_write_enable_reg = DFFE(NB1_q_a[7]_PORT_A_write_enable, NB1_q_a[7]_clock_0, , , );
NB1_q_a[7]_PORT_B_write_enable = PB1L33;
NB1_q_a[7]_PORT_B_write_enable_reg = DFFE(NB1_q_a[7]_PORT_B_write_enable, NB1_q_a[7]_clock_1, , , );
NB1_q_a[7]_clock_0 = GLOBAL(CLK);
NB1_q_a[7]_clock_1 = GLOBAL(A1L51);
NB1_q_a[7]_PORT_A_data_out = MEMORY(NB1_q_a[7]_PORT_A_data_in_reg, NB1_q_a[7]_PORT_B_data_in_reg, NB1_q_a[7]_PORT_A_address_reg, NB1_q_a[7]_PORT_B_address_reg, NB1_q_a[7]_PORT_A_write_enable_reg, NB1_q_a[7]_PORT_B_write_enable_reg, , , NB1_q_a[7]_clock_0, NB1_q_a[7]_clock_1, , , , );
NB1_q_a[0] = NB1_q_a[7]_PORT_A_data_out[3];

--NB1_q_a[1] is DPRAM:u1|altsyncram:altsyncram_component|altsyncram_d071:auto_generated|altsyncram_56e2:altsyncram1|q_a[1] at M4K_X17_Y10