📄 tennis.map.rpt
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+-----------+
TENNIS
|-- cou4:uah
|-- lpm_counter:qqout_rtl_0
|-- cntr_2p7:auto_generated
|-- cou10:ual
|-- lpm_counter:qqout_rtl_1
|-- cntr_2p7:auto_generated
|-- ball:uball
|-- board:ubda
|-- board:ubdb
|-- cou4:ubh
|-- lpm_counter:qqout_rtl_2
|-- cntr_2p7:auto_generated
|-- cou10:ubl
|-- lpm_counter:qqout_rtl_3
|-- cntr_2p7:auto_generated
|-- ballctrl:ucpu
|-- sound:usound
|-- mway:uway
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------+
; |TENNIS ; 45 (0) ; 32 ; 0 ; 31 ; 0 ; 13 (0) ; 4 (0) ; 28 (0) ; 16 (0) ; |TENNIS ;
; |ball:uball| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 10 (10) ; 0 (0) ; |TENNIS|ball:uball ;
; |ballctrl:ucpu| ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 0 (0) ; 0 (0) ; |TENNIS|ballctrl:ucpu ;
; |board:ubda| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; |TENNIS|board:ubda ;
; |board:ubdb| ; 3 (3) ; 2 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; |TENNIS|board:ubdb ;
; |cou10:ual| ; 6 (2) ; 5 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 4 (0) ; 4 (0) ; |TENNIS|cou10:ual ;
; |lpm_counter:qqout_rtl_1| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |TENNIS|cou10:ual|lpm_counter:qqout_rtl_1 ;
; |cntr_2p7:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |TENNIS|cou10:ual|lpm_counter:qqout_rtl_1|cntr_2p7:auto_generated ;
; |cou10:ubl| ; 6 (2) ; 5 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 4 (0) ; 4 (0) ; |TENNIS|cou10:ubl ;
; |lpm_counter:qqout_rtl_3| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |TENNIS|cou10:ubl|lpm_counter:qqout_rtl_3 ;
; |cntr_2p7:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |TENNIS|cou10:ubl|lpm_counter:qqout_rtl_3|cntr_2p7:auto_generated ;
; |cou4:uah| ; 5 (1) ; 4 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (0) ; 4 (0) ; |TENNIS|cou4:uah ;
; |lpm_counter:qqout_rtl_0| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |TENNIS|cou4:uah|lpm_counter:qqout_rtl_0 ;
; |cntr_2p7:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |TENNIS|cou4:uah|lpm_counter:qqout_rtl_0|cntr_2p7:auto_generated ;
; |cou4:ubh| ; 5 (1) ; 4 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (0) ; 4 (0) ; |TENNIS|cou4:ubh ;
; |lpm_counter:qqout_rtl_2| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |TENNIS|cou4:ubh|lpm_counter:qqout_rtl_2 ;
; |cntr_2p7:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |TENNIS|cou4:ubh|lpm_counter:qqout_rtl_2|cntr_2p7:auto_generated ;
; |mway:uway| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |TENNIS|mway:uway ;
; |sound:usound| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; |TENNIS|sound:usound ;
+------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/EDA_SOPC6_12/Chpt10/EXPT10_2_TENNIS/TENNIS.map.eqn.
+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+--------------------------------------------------------------+-----------------+
; File Name ; Used in Netlist ;
+--------------------------------------------------------------+-----------------+
; BALL.VHD ; yes ;
; BALLCTRL.VHD ; yes ;
; BOARD.VHD ; yes ;
; COU10.VHD ; yes ;
; COU4.VHD ; yes ;
; MWAY.VHD ; yes ;
; SOUND.VHD ; yes ;
; TENNIS.VHD ; yes ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf ; yes ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes ;
; D:/EDA_SOPC6_12/Chpt10/EXPT10_2_TENNIS/db/cntr_2p7.tdf ; yes ;
+--------------------------------------------------------------+-----------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 45 ;
; Total combinational functions ; 41 ;
; Total 4-input functions ; 7 ;
; Total 3-input functions ; 10 ;
; Total 2-input functions ; 6 ;
; Total 1-input functions ; 16 ;
; Total 0-input functions ; 2 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 32 ;
; Total logic cells in carry chains ; 16 ;
; I/O pins ; 31 ;
; Maximum fan-out node ; clr ;
; Maximum fan-out ; 21 ;
; Total fan-out ; 220 ;
; Average fan-out ; 2.89 ;
+-----------------------------------+---------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Tue Aug 02 08:18:28 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off TENNIS -c TENNIS
Info: Found 2 design units, including 1 entities, in source file BALL.VHD
Info: Found design unit 1: ball-ful
Info: Found entity 1: ball
Info: Found 2 design units, including 1 entities, in source file BALLCTRL.VHD
Info: Found design unit 1: ballctrl-ful
Info: Found entity 1: ballctrl
Info: Found 2 design units, including 1 entities, in source file BOARD.VHD
Info: Found design unit 1: board-ful
Info: Found entity 1: board
Info: Found 2 design units, including 1 entities, in source file COU10.VHD
Info: Found design unit 1: cou10-ful
Info: Found entity 1: cou10
Info: Found 2 design units, including 1 entities, in source file COU4.VHD
Info: Found design unit 1: cou4-ful
Info: Found entity 1: cou4
Info: Found 2 design units, including 1 entities, in source file MWAY.VHD
Info: Found design unit 1: mway-ful
Info: Found entity 1: mway
Info: Found 2 design units, including 1 entities, in source file SOUND.VHD
Info: Found design unit 1: sound-ful
Info: Found entity 1: sound
Info: Found 2 design units, including 1 entities, in source file TENNIS.VHD
Info: Found design unit 1: TENNIS-ful
Info: Found entity 1: TENNIS
Warning: VHDL Process Statement warning at COU4.VHD(31): signal qqout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at COU10.VHD(30): signal qqout is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at BALLCTRL.VHD(33): signal ser is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at BALLCTRL.VHD(25): signal or variable serve may not be assigned a new value in every possible path through the Process Statement. Signal or variable serve holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at BALLCTRL.VHD(25): signal or variable ballen may not be assigned a new value in every possible path through the Process Statement. Signal or variable ballen holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at MWAY.VHD(11): signal or variable way may not be assigned a new value in every possible path through the Process Statement. Signal or variable way holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at BALL.VHD(29): signal lamp is in statement, but is not in sensitivity list
Info: Ignored 3 buffer(s)
Info: Ignored 3 SOFT buffer(s)
Info: Inferred 4 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: cou4:uah|qqout[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: cou10:ual|qqout[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: cou4:ubh|qqout[0]~4
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: cou10:ubl|qqout[0]~4
Info: Found 1 design units, including 1 entities, in source file ../../../altera/quartus41/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_2p7.tdf
Info: Found entity 1: cntr_2p7
Info: Registers with preset signals will power-up high
Info: Implemented 76 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 26 output pins
Info: Implemented 45 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Processing ended: Tue Aug 02 08:18:32 2005
Info: Elapsed time: 00:00:04
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