arthoper.v

4-7segment led display Verilog code. Implemented at Stratix EP1S25 DSP development board.

//	File:         ARTHOPER.v
//	
//	Description:  This module relize the 4 bits arithmetic operation,
//                including PLUS, MINUS, MULTIPLY. The operation result
//                output via Dual 7-segment display.
//
//  Input:        sw[3] -- 3bits.Each pushbutton signal is defined as a logic 1 
//                         when in its normal state; when pressed, it 
//                         becomes a logic 0; when released it goes back 
//                         to logic 1.
//                sw3p[8]--8bits.DIP switches drive a logic 1 to the Stratix 
//                         device when in the off position, and a logic 
//                         0 into the Stratix device when in the on position.
//                clk_in --80MHZ.
//                ar     --Reset signal.
//
//  Output:       hex0_output[7]--7bits.High character of 7-segment display;
//                hex1_output[7]--7bits.Low charactoer of 7-segment display;
//                op_rst        --Operating result;
//
//	Author(s):		  Xiaohu Zhang
//
//	Date Created:	January 29 2007
//
//	Version:      1.0		1/29/2007 Original version
//
//	History:	     Date		    Author(s)			  Memo
//                1/29/2007	Xiaohu Zhang	

`timescale	10us/1us

module ARTH_OPER(sw, 
                 sw3p, 
                 op_rst, 
                 hex0_output, 
                 hex1_output, 
                 clk_in, 
                 ar
                 );
    `define OP_PLUS   3'b110
    `define OP_MINUS  3'b101
    `define OP_MULT   3'b011
    
    input  [2:0] sw;
    input  [7:0] sw3p;
    input  clk_in;
    input  ar;
    
    output [6:0] hex0_output;
    output [6:0] hex1_output;
    output [7:0] op_rst;
    
    reg    [3:0] hex0_input;
    reg    [3:0] hex1_input;
    reg    [7:0] op_rst;         // The result of operation
    reg    clk_out;
    
    //assign hex0_input = sw3p[7:4];
    //assign hex1_input = sw3p[3:0];
    
    BCD27SegDisp TB_BCD47D0(hex0_input, hex0_output, ar);
    BCD27SegDisp TB_BCD47D1(hex1_input, hex1_output, ar);
    
    always @(clk_in or ar or sw)
    begin
    if(~ar)
        begin
            op_rst = 8'b0;
            hex0_input = op_rst[7:4];
            hex1_input = op_rst[3:0];
        end
    else
        begin
            case(sw)
                `OP_PLUS:// + operation
                    begin
                        op_rst = sw3p[7:4] + sw3p[3:0]; 
                    end
                    
                `OP_MINUS:// - operation
                    begin
                        op_rst = sw3p[7:4] - sw3p[3:0]; 
                    end
                    
                `OP_MULT:// * operation
                    begin
                        op_rst = sw3p[7:4] * sw3p[3:0]; 
                    end
                                      
                default:// + operation
                    begin
                        op_rst = sw3p[7:4] + sw3p[3:0]; 
                    end
            endcase
            
            hex0_input = op_rst[7:4];
            hex1_input = op_rst[3:0];
        end// end of else begin
        
     end // end of always begin
    
endmodule