led47disp.v

4-7segment led display Verilog code. Implemented at Stratix EP1S25 DSP development board.

//	File:         LED47DISP.v
//	
//	Description:  BCD code to 7 segment LED display.
//                en-----'1' is ENABLE,
//                       '0' is DISABLE;
//                input--4bits data;
//                output-7bits segment,
//                       '0' segment is ACTIVE,
//                       '1' segment is NON-ACTIVE;
//
//                    a        
//                  +---+       
//                 f|   |b      'gfedcba'
//                  +-g-+        |||||||
//                 e|   |c    0b'0000000'
//                  +---+
//                    d
//
//	Author(s):		  Xiaohu Zhang
//
//	Date Created:	January 28 2007
//
//	Version:      1.0		1/20/2007 Original version
//
//	History:	     Date		    Author(s)			  Memo
//                1/28/2007	Xiaohu Zhang	

`timescale	10us/1us

module BCD27SegDisp(data_in, data_out, en);

    `define    ENABLE    1
    `define    DISABLE   0
        
    input  [3:0]data_in;
    input  en;
    output [6:0]data_out;
    reg    [6:0]data_out;
    
    always@(data_in or en)
        begin
            data_out = 7'b1111111;                  //Clear
            
            if(en == `ENABLE)
                case(data_in)
                    4'b0000: data_out = 7'b1000000; //0
                    4'b0001: data_out = 7'b1111001; //1
                    4'b0010: data_out = 7'b0100100; //2
                    4'b0011: data_out = 7'b0110000; //3
                    4'b0100: data_out = 7'b0011001; //4
                    4'b0101: data_out = 7'b0010010; //5
                    4'b0110: data_out = 7'b0000011; //6
                    4'b0111: data_out = 7'b1111000; //7
                    4'b1000: data_out = 7'b0000000; //8
                    4'b1001: data_out = 7'b0011000; //9
                    4'b1010: data_out = 7'b0001000; //A
                    4'b1011: data_out = 7'b0000011; //B
                    4'b1100: data_out = 7'b0100111; //C
                    4'b1101: data_out = 7'b0100001; //D
                    4'b1110: data_out = 7'b0000110; //E
                    4'b1111: data_out = 7'b0001110; //F
                    default: data_out = 7'b1111111; //Clear
                endcase
            
            else if(en == `DISABLE)
                data_out = 7'b1111111;//Clear
        end
endmodule