encoder_time_post.vhd

应用VHDL设计的8b10b 编码器

      I4 => data_in_4_II_UIM,
      I5 => NlwInverterSignal_pds6_MC_D2_PT_3_IN5,
      I6 => NlwInverterSignal_pds6_MC_D2_PT_3_IN6,
      O => pds6_MC_D2_PT_3
    );
  pds6_MC_D2_105 : X_OR4
    port map (
      I0 => pds6_MC_D2_PT_0,
      I1 => pds6_MC_D2_PT_1,
      I2 => pds6_MC_D2_PT_2,
      I3 => pds6_MC_D2_PT_3,
      O => pds6_MC_D2
    );
  pds6_MC_XOR : X_XOR2
    port map (
      I0 => pds6_MC_D1,
      I1 => pds6_MC_D2,
      O => pds6_MC_D
    );
  k_char_II_UIM_106 : X_BUF
    port map (
      I => k_char,
      O => k_char_II_UIM
    );
  N_PZ_166_107 : X_BUF
    port map (
      I => N_PZ_166_MC_Q,
      O => N_PZ_166
    );
  N_PZ_166_MC_REG : X_BUF
    port map (
      I => N_PZ_166_MC_D,
      O => N_PZ_166_MC_Q
    );
  N_PZ_166_MC_D1_108 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_166_MC_D1
    );
  N_PZ_166_MC_D2_PT_0_109 : X_AND2
    port map (
      I0 => N_PZ_154,
      I1 => N_PZ_154,
      O => N_PZ_166_MC_D2_PT_0
    );
  N_PZ_166_MC_D2_PT_1_110 : X_AND2
    port map (
      I0 => NlwInverterSignal_N_PZ_166_MC_D2_PT_1_IN0,
      I1 => NlwInverterSignal_N_PZ_166_MC_D2_PT_1_IN1,
      O => N_PZ_166_MC_D2_PT_1
    );
  N_PZ_166_MC_D2_PT_2_111 : X_AND3
    port map (
      I0 => data_in_5_II_UIM,
      I1 => data_in_6_II_UIM,
      I2 => data_in_7_II_UIM,
      O => N_PZ_166_MC_D2_PT_2
    );
  N_PZ_166_MC_D2_112 : X_OR3
    port map (
      I0 => N_PZ_166_MC_D2_PT_0,
      I1 => N_PZ_166_MC_D2_PT_1,
      I2 => N_PZ_166_MC_D2_PT_2,
      O => N_PZ_166_MC_D2
    );
  N_PZ_166_MC_XOR : X_XOR2
    port map (
      I0 => N_PZ_166_MC_D1,
      I1 => N_PZ_166_MC_D2,
      O => N_PZ_166_MC_D
    );
  data_in_5_II_UIM_113 : X_BUF
    port map (
      I => data_in(5),
      O => data_in_5_II_UIM
    );
  data_in_6_II_UIM_114 : X_BUF
    port map (
      I => data_in(6),
      O => data_in_6_II_UIM
    );
  data_in_7_II_UIM_115 : X_BUF
    port map (
      I => data_in(7),
      O => data_in_7_II_UIM
    );
  encoded_data_0_Q : X_BUF
    port map (
      I => encoded_data_0_MC_Q,
      O => encoded_data(0)
    );
  encoded_data_0_MC_Q_116 : X_BUF
    port map (
      I => encoded_data_0_MC_Q_tsim_ireg_Q,
      O => encoded_data_0_MC_Q
    );
  encoded_data_0_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => encoded_data_0_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => PRLD,
      O => encoded_data_0_MC_Q_tsim_ireg_Q
    );
  encoded_data_0_MC_D1_117 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => encoded_data_0_MC_D1
    );
  encoded_data_0_MC_D2_PT_0_118 : X_AND2
    port map (
      I0 => NlwInverterSignal_encoded_data_0_MC_D2_PT_0_IN0,
      I1 => encoded_data_0_MC_UIM,
      O => encoded_data_0_MC_D2_PT_0
    );
  encoded_data_0_MC_D2_PT_1_119 : X_AND8
    port map (
      I0 => data_in_5_II_UIM,
      I1 => NlwInverterSignal_encoded_data_0_MC_D2_PT_1_IN1,
      I2 => NlwInverterSignal_encoded_data_0_MC_D2_PT_1_IN2,
      I3 => enc_8b10b_prs_state_fft2,
      I4 => NlwInverterSignal_encoded_data_0_MC_D2_PT_1_IN4,
      I5 => enc_8b10b_prs_state_fft1,
      I6 => NlwInverterSignal_encoded_data_0_MC_D2_PT_1_IN6,
      I7 => rst_II_UIM,
      O => encoded_data_0_MC_D2_PT_1
    );
  encoded_data_0_MC_D2_PT_2_120 : X_AND8
    port map (
      I0 => NlwInverterSignal_encoded_data_0_MC_D2_PT_2_IN0,
      I1 => data_in_6_II_UIM,
      I2 => NlwInverterSignal_encoded_data_0_MC_D2_PT_2_IN2,
      I3 => enc_8b10b_prs_state_fft2,
      I4 => NlwInverterSignal_encoded_data_0_MC_D2_PT_2_IN4,
      I5 => enc_8b10b_prs_state_fft1,
      I6 => NlwInverterSignal_encoded_data_0_MC_D2_PT_2_IN6,
      I7 => rst_II_UIM,
      O => encoded_data_0_MC_D2_PT_2
    );
  encoded_data_0_MC_D2_PT_3_121 : X_AND16
    port map (
      I0 => data_in_5_II_UIM,
      I1 => data_in_6_II_UIM,
      I2 => data_in_7_II_UIM,
      I3 => enc_8b10b_prs_state_fft2,
      I4 => NlwInverterSignal_encoded_data_0_MC_D2_PT_3_IN4,
      I5 => enc_8b10b_prs_state_fft1,
      I6 => NlwInverterSignal_encoded_data_0_MC_D2_PT_3_IN6,
      I7 => rst_II_UIM,
      I8 => k_char_II_UIM,
      I9 => VCC,
      I10 => VCC,
      I11 => VCC,
      I12 => VCC,
      I13 => VCC,
      I14 => VCC,
      I15 => VCC,
      O => encoded_data_0_MC_D2_PT_3
    );
  encoded_data_0_MC_D2_PT_4_122 : X_AND16
    port map (
      I0 => data_in_5_II_UIM,
      I1 => data_in_6_II_UIM,
      I2 => data_in_7_II_UIM,
      I3 => enc_8b10b_prs_state_fft2,
      I4 => NlwInverterSignal_encoded_data_0_MC_D2_PT_4_IN4,
      I5 => enc_8b10b_prs_state_fft1,
      I6 => NlwInverterSignal_encoded_data_0_MC_D2_PT_4_IN6,
      I7 => rst_II_UIM,
      I8 => s_term,
      I9 => VCC,
      I10 => VCC,
      I11 => VCC,
      I12 => VCC,
      I13 => VCC,
      I14 => VCC,
      I15 => VCC,
      O => encoded_data_0_MC_D2_PT_4
    );
  encoded_data_0_MC_D2_123 : X_OR5
    port map (
      I0 => encoded_data_0_MC_D2_PT_0,
      I1 => encoded_data_0_MC_D2_PT_1,
      I2 => encoded_data_0_MC_D2_PT_2,
      I3 => encoded_data_0_MC_D2_PT_3,
      I4 => encoded_data_0_MC_D2_PT_4,
      O => encoded_data_0_MC_D2
    );
  encoded_data_0_MC_XOR : X_XOR2
    port map (
      I0 => encoded_data_0_MC_D1,
      I1 => encoded_data_0_MC_D2,
      O => encoded_data_0_MC_D
    );
  encoded_data_0_MC_UIM_124 : X_BUF
    port map (
      I => encoded_data_0_MC_Q_tsim_ireg_Q,
      O => encoded_data_0_MC_UIM
    );
  s_term_125 : X_BUF
    port map (
      I => s_term_MC_Q,
      O => s_term
    );
  s_term_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => s_term_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => PRLD,
      O => s_term_MC_Q
    );
  s_term_MC_D1_126 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => s_term_MC_D1
    );
  s_term_MC_D2_PT_0_127 : X_AND2
    port map (
      I0 => NlwInverterSignal_s_term_MC_D2_PT_0_IN0,
      I1 => NlwInverterSignal_s_term_MC_D2_PT_0_IN1,
      O => s_term_MC_D2_PT_0
    );
  s_term_MC_D2_PT_1_128 : X_AND2
    port map (
      I0 => rst_II_UIM,
      I1 => s_func_prs_state_ffd1,
      O => s_term_MC_D2_PT_1
    );
  s_term_MC_D2_PT_2_129 : X_AND2
    port map (
      I0 => rst_II_UIM,
      I1 => NlwInverterSignal_s_term_MC_D2_PT_2_IN1,
      O => s_term_MC_D2_PT_2
    );
  s_term_MC_D2_PT_3_130 : X_AND2
    port map (
      I0 => NlwInverterSignal_s_term_MC_D2_PT_3_IN0,
      I1 => NlwInverterSignal_s_term_MC_D2_PT_3_IN1,
      O => s_term_MC_D2_PT_3
    );
  s_term_MC_D2_PT_4_131 : X_AND3
    port map (
      I0 => data_in_3_II_UIM,
      I1 => rst_II_UIM,
      I2 => NlwInverterSignal_s_term_MC_D2_PT_4_IN2,
      O => s_term_MC_D2_PT_4
    );
  s_term_MC_D2_PT_5_132 : X_AND3
    port map (
      I0 => NlwInverterSignal_s_term_MC_D2_PT_5_IN0,
      I1 => NlwInverterSignal_s_term_MC_D2_PT_5_IN1,
      I2 => rst_II_UIM,
      O => s_term_MC_D2_PT_5
    );
  s_term_MC_D2_PT_6_133 : X_AND3
    port map (
      I0 => data_in_4_II_UIM,
      I1 => rst_II_UIM,
      I2 => N_PZ_174,
      O => s_term_MC_D2_PT_6
    );
  s_term_MC_D2_PT_7_134 : X_AND3
    port map (
      I0 => NlwInverterSignal_s_term_MC_D2_PT_7_IN0,
      I1 => rst_II_UIM,
      I2 => NlwInverterSignal_s_term_MC_D2_PT_7_IN2,
      O => s_term_MC_D2_PT_7
    );
  s_term_MC_D2_PT_8_135 : X_AND3
    port map (
      I0 => nds6,
      I1 => rst_II_UIM,
      I2 => NlwInverterSignal_s_term_MC_D2_PT_8_IN2,
      O => s_term_MC_D2_PT_8
    );
  s_term_MC_D2_PT_9_136 : X_AND3
    port map (
      I0 => pds6,
      I1 => rst_II_UIM,
      I2 => NlwInverterSignal_s_term_MC_D2_PT_9_IN2,
      O => s_term_MC_D2_PT_9
    );
  s_term_MC_D2_PT_10_137 : X_AND4
    port map (
      I0 => data_in_0_II_UIM,
      I1 => data_in_1_II_UIM,
      I2 => data_in_2_II_UIM,
      I3 => rst_II_UIM,
      O => s_term_MC_D2_PT_10
    );
  s_term_MC_D2_PT_11_138 : X_AND4
    port map (
      I0 => NlwInverterSignal_s_term_MC_D2_PT_11_IN0,
      I1 => NlwInverterSignal_s_term_MC_D2_PT_11_IN1,
      I2 => NlwInverterSignal_s_term_MC_D2_PT_11_IN2,
      I3 => rst_II_UIM,
      O => s_term_MC_D2_PT_11
    );
  s_term_MC_D2_PT_12_139 : X_AND5
    port map (
      I0 => dis_in_II_UIM,
      I1 => NlwInverterSignal_s_term_MC_D2_PT_12_IN1,
      I2 => NlwInverterSignal_s_term_MC_D2_PT_12_IN2,
      I3 => rst_II_UIM,
      I4 => N_PZ_174,
      O => s_term_MC_D2_PT_12
    );
  s_term_MC_D2_140 : X_OR16
    port map (
      I0 => s_term_MC_D2_PT_0,
      I1 => s_term_MC_D2_PT_1,
      I2 => s_term_MC_D2_PT_2,
      I3 => s_term_MC_D2_PT_3,
      I4 => s_term_MC_D2_PT_4,
      I5 => s_term_MC_D2_PT_5,
      I6 => s_term_MC_D2_PT_6,
      I7 => s_term_MC_D2_PT_7,
      I8 => s_term_MC_D2_PT_8,
      I9 => s_term_MC_D2_PT_9,
      I10 => s_term_MC_D2_PT_10,
      I11 => s_term_MC_D2_PT_11,
      I12 => s_term_MC_D2_PT_12,
      I13 => GND,
      I14 => GND,
      I15 => GND,
      O => s_term_MC_D2
    );
  s_term_MC_XOR : X_XOR2
    port map (
      I0 => NlwInverterSignal_s_term_MC_XOR_IN0,
      I1 => s_term_MC_D2,
      O => s_term_MC_D
    );
  N_PZ_194_141 : X_BUF
    port map (
      I => N_PZ_194_MC_Q,
      O => N_PZ_194
    );
  N_PZ_194_MC_REG : X_BUF
    port map (
      I => N_PZ_194_MC_D,
      O => N_PZ_194_MC_Q
    );
  N_PZ_194_MC_D1_142 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_194_MC_D1
    );
  N_PZ_194_MC_D2_PT_0_143 : X_AND2
    port map (
      I0 => NlwInverterSignal_N_PZ_194_MC_D2_PT_0_IN0,
      I1 => NlwInverterSignal_N_PZ_194_MC_D2_PT_0_IN1,
      O => N_PZ_194_MC_D2_PT_0
    );
  N_PZ_194_MC_D2_PT_1_144 : X_AND3
    port map (
      I0 => enc_8b10b_prs_state_fft2,
      I1 => NlwInverterSignal_N_PZ_194_MC_D2_PT_1_IN1,
      I2 => NlwInverterSignal_N_PZ_194_MC_D2_P