encoder_time_post.vhd

应用VHDL设计的8b10b 编码器

      I0 => dis_func_prs_state_ffd2_MC_D1,
      I1 => dis_func_prs_state_ffd2_MC_D2,
      O => dis_func_prs_state_ffd2_MC_D
    );
  dis_func_prs_state_ffd1_18 : X_BUF
    port map (
      I => dis_func_prs_state_ffd1_MC_Q,
      O => dis_func_prs_state_ffd1
    );
  dis_func_prs_state_ffd1_MC_R_OR_PRLD_19 : X_OR2
    port map (
      I0 => FOOBAR2_ctinst_7,
      I1 => PRLD,
      O => dis_func_prs_state_ffd1_MC_R_OR_PRLD
    );
  dis_func_prs_state_ffd1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => dis_func_prs_state_ffd1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => dis_func_prs_state_ffd1_MC_R_OR_PRLD,
      O => dis_func_prs_state_ffd1_MC_Q
    );
  dis_func_prs_state_ffd1_MC_D1_20 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => dis_func_prs_state_ffd1_MC_D1
    );
  dis_func_prs_state_ffd1_MC_D2_PT_0_21 : X_AND2
    port map (
      I0 => NlwInverterSignal_dis_func_prs_state_ffd1_MC_D2_PT_0_IN0,
      I1 => dis_func_prs_state_ffd1,
      O => dis_func_prs_state_ffd1_MC_D2_PT_0
    );
  dis_func_prs_state_ffd1_MC_D2_PT_1_22 : X_AND3
    port map (
      I0 => NlwInverterSignal_dis_func_prs_state_ffd1_MC_D2_PT_1_IN0,
      I1 => NlwInverterSignal_dis_func_prs_state_ffd1_MC_D2_PT_1_IN1,
      I2 => prs_state_fft1,
      O => dis_func_prs_state_ffd1_MC_D2_PT_1
    );
  dis_func_prs_state_ffd1_MC_D2_23 : X_OR2
    port map (
      I0 => dis_func_prs_state_ffd1_MC_D2_PT_0,
      I1 => dis_func_prs_state_ffd1_MC_D2_PT_1,
      O => dis_func_prs_state_ffd1_MC_D2
    );
  dis_func_prs_state_ffd1_MC_XOR : X_XOR2
    port map (
      I0 => dis_func_prs_state_ffd1_MC_D1,
      I1 => dis_func_prs_state_ffd1_MC_D2,
      O => dis_func_prs_state_ffd1_MC_D
    );
  prs_state_fft2_24 : X_BUF
    port map (
      I => prs_state_fft2_MC_Q,
      O => prs_state_fft2
    );
  prs_state_fft2_MC_R_OR_PRLD_25 : X_OR2
    port map (
      I0 => FOOBAR2_ctinst_7,
      I1 => PRLD,
      O => prs_state_fft2_MC_R_OR_PRLD
    );
  prs_state_fft2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => prs_state_fft2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => prs_state_fft2_MC_R_OR_PRLD,
      O => prs_state_fft2_MC_Q
    );
  prs_state_fft2_MC_D1_26 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => prs_state_fft2_MC_D1
    );
  prs_state_fft2_MC_D2_PT_0_27 : X_AND3
    port map (
      I0 => prs_state_fft2,
      I1 => prs_state_fft1,
      I2 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_0_IN2,
      O => prs_state_fft2_MC_D2_PT_0
    );
  prs_state_fft2_MC_D2_PT_1_28 : X_AND5
    port map (
      I0 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_1_IN0,
      I1 => prs_state_fft1,
      I2 => enc_8b10b_prs_state_fft2,
      I3 => NlwInverterSignal_prs_state_fft2_MC_D2_PT_1_IN3,
      I4 => enc_8b10b_prs_state_fft1,
      O => prs_state_fft2_MC_D2_PT_1
    );
  prs_state_fft2_MC_D2_29 : X_OR2
    port map (
      I0 => prs_state_fft2_MC_D2_PT_0,
      I1 => prs_state_fft2_MC_D2_PT_1,
      O => prs_state_fft2_MC_D2
    );
  prs_state_fft2_MC_D_30 : X_XOR2
    port map (
      I0 => prs_state_fft2_MC_D_TFF,
      I1 => prs_state_fft2_MC_Q,
      O => prs_state_fft2_MC_D
    );
  prs_state_fft2_MC_XOR : X_XOR2
    port map (
      I0 => prs_state_fft2_MC_D1,
      I1 => prs_state_fft2_MC_D2,
      O => prs_state_fft2_MC_D_TFF
    );
  prs_state_fft1_31 : X_BUF
    port map (
      I => prs_state_fft1_MC_Q,
      O => prs_state_fft1
    );
  prs_state_fft1_MC_R_OR_PRLD_32 : X_OR2
    port map (
      I0 => FOOBAR2_ctinst_7,
      I1 => PRLD,
      O => prs_state_fft1_MC_R_OR_PRLD
    );
  prs_state_fft1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => prs_state_fft1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => prs_state_fft1_MC_R_OR_PRLD,
      O => prs_state_fft1_MC_Q
    );
  prs_state_fft1_MC_D1_33 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => prs_state_fft1_MC_D1
    );
  prs_state_fft1_MC_D2_PT_0_34 : X_AND2
    port map (
      I0 => frame_in_II_UIM,
      I1 => N_PZ_154,
      O => prs_state_fft1_MC_D2_PT_0
    );
  prs_state_fft1_MC_D2_PT_1_35 : X_AND3
    port map (
      I0 => prs_state_fft2,
      I1 => prs_state_fft1,
      I2 => NlwInverterSignal_prs_state_fft1_MC_D2_PT_1_IN2,
      O => prs_state_fft1_MC_D2_PT_1
    );
  prs_state_fft1_MC_D2_36 : X_OR2
    port map (
      I0 => prs_state_fft1_MC_D2_PT_0,
      I1 => prs_state_fft1_MC_D2_PT_1,
      O => prs_state_fft1_MC_D2
    );
  prs_state_fft1_MC_D_37 : X_XOR2
    port map (
      I0 => prs_state_fft1_MC_D_TFF,
      I1 => prs_state_fft1_MC_Q,
      O => prs_state_fft1_MC_D
    );
  prs_state_fft1_MC_XOR : X_XOR2
    port map (
      I0 => prs_state_fft1_MC_D1,
      I1 => prs_state_fft1_MC_D2,
      O => prs_state_fft1_MC_D_TFF
    );
  frame_in_II_UIM_38 : X_BUF
    port map (
      I => frame_in,
      O => frame_in_II_UIM
    );
  N_PZ_154_39 : X_BUF
    port map (
      I => N_PZ_154_MC_Q,
      O => N_PZ_154
    );
  N_PZ_154_MC_REG : X_BUF
    port map (
      I => N_PZ_154_MC_D,
      O => N_PZ_154_MC_Q
    );
  N_PZ_154_MC_D1_PT_0_40 : X_AND2
    port map (
      I0 => NlwInverterSignal_N_PZ_154_MC_D1_PT_0_IN0,
      I1 => NlwInverterSignal_N_PZ_154_MC_D1_PT_0_IN1,
      O => N_PZ_154_MC_D1_PT_0
    );
  N_PZ_154_MC_D1_41 : X_OR2
    port map (
      I0 => N_PZ_154_MC_D1_PT_0,
      I1 => N_PZ_154_MC_D1_PT_0,
      O => N_PZ_154_MC_D1
    );
  N_PZ_154_MC_D2_42 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => N_PZ_154_MC_D2
    );
  N_PZ_154_MC_XOR : X_XOR2
    port map (
      I0 => N_PZ_154_MC_D1,
      I1 => N_PZ_154_MC_D2,
      O => N_PZ_154_MC_D
    );
  clk_II_FCLK_43 : X_BUF
    port map (
      I => clk,
      O => clk_II_FCLK
    );
  enc_8b10b_prs_state_fft2_44 : X_BUF
    port map (
      I => enc_8b10b_prs_state_fft2_MC_Q,
      O => enc_8b10b_prs_state_fft2
    );
  enc_8b10b_prs_state_fft2_MC_R_OR_PRLD_45 : X_OR2
    port map (
      I0 => FOOBAR2_ctinst_7,
      I1 => PRLD,
      O => enc_8b10b_prs_state_fft2_MC_R_OR_PRLD
    );
  enc_8b10b_prs_state_fft2_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => enc_8b10b_prs_state_fft2_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => enc_8b10b_prs_state_fft2_MC_R_OR_PRLD,
      O => enc_8b10b_prs_state_fft2_MC_Q
    );
  enc_8b10b_prs_state_fft2_MC_D1_PT_0_46 : X_AND2
    port map (
      I0 => NlwInverterSignal_enc_8b10b_prs_state_fft2_MC_D1_PT_0_IN0,
      I1 => enc_8b10b_prs_state_fft1,
      O => enc_8b10b_prs_state_fft2_MC_D1_PT_0
    );
  enc_8b10b_prs_state_fft2_MC_D1_47 : X_OR2
    port map (
      I0 => enc_8b10b_prs_state_fft2_MC_D1_PT_0,
      I1 => enc_8b10b_prs_state_fft2_MC_D1_PT_0,
      O => enc_8b10b_prs_state_fft2_MC_D1
    );
  enc_8b10b_prs_state_fft2_MC_D2_48 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => enc_8b10b_prs_state_fft2_MC_D2
    );
  enc_8b10b_prs_state_fft2_MC_D_49 : X_XOR2
    port map (
      I0 => enc_8b10b_prs_state_fft2_MC_D_TFF,
      I1 => enc_8b10b_prs_state_fft2_MC_Q,
      O => enc_8b10b_prs_state_fft2_MC_D
    );
  enc_8b10b_prs_state_fft2_MC_XOR : X_XOR2
    port map (
      I0 => enc_8b10b_prs_state_fft2_MC_D1,
      I1 => enc_8b10b_prs_state_fft2_MC_D2,
      O => enc_8b10b_prs_state_fft2_MC_D_TFF
    );
  enc_8b10b_prs_state_fft3_50 : X_BUF
    port map (
      I => enc_8b10b_prs_state_fft3_MC_Q,
      O => enc_8b10b_prs_state_fft3
    );
  enc_8b10b_prs_state_fft3_MC_R_OR_PRLD_51 : X_OR2
    port map (
      I0 => FOOBAR2_ctinst_7,
      I1 => PRLD,
      O => enc_8b10b_prs_state_fft3_MC_R_OR_PRLD
    );
  enc_8b10b_prs_state_fft3_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => enc_8b10b_prs_state_fft3_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => enc_8b10b_prs_state_fft3_MC_R_OR_PRLD,
      O => enc_8b10b_prs_state_fft3_MC_Q
    );
  enc_8b10b_prs_state_fft3_MC_D1_52 : X_OR2
    port map (
      I0 => GND,
      I1 => GND,
      O => enc_8b10b_prs_state_fft3_MC_D1
    );
  enc_8b10b_prs_state_fft3_MC_D2_PT_0_53 : X_AND3
    port map (
      I0 => enc_8b10b_prs_state_fft2,
      I1 => NlwInverterSignal_enc_8b10b_prs_state_fft3_MC_D2_PT_0_IN1,
      I2 => enc_8b10b_prs_state_fft1,
      O => enc_8b10b_prs_state_fft3_MC_D2_PT_0
    );
  enc_8b10b_prs_state_fft3_MC_D2_PT_1_54 : X_AND4
    port map (
      I0 => prs_state_fft2,
      I1 => NlwInverterSignal_enc_8b10b_prs_state_fft3_MC_D2_PT_1_IN1,
      I2 => enc_8b10b_prs_state_fft3,
      I3 => NlwInverterSignal_enc_8b10b_prs_state_fft3_MC_D2_PT_1_IN3,
      O => enc_8b10b_prs_state_fft3_MC_D2_PT_1
    );
  enc_8b10b_prs_state_fft3_MC_D2_PT_2_55 : X_AND4
    port map (
      I0 => NlwInverterSignal_enc_8b10b_prs_state_fft3_MC_D2_PT_2_IN0,
      I1 => NlwInverterSignal_enc_8b10b_prs_state_fft3_MC_D2_PT_2_IN1,
      I2 => enc_8b10b_prs_state_fft3,
      I3 => NlwInverterSignal_enc_8b10b_prs_state_fft3_MC_D2_PT_2_IN3,
      O => enc_8b10b_prs_state_fft3_MC_D2_PT_2
    );
  enc_8b10b_prs_state_fft3_MC_D2_56 : X_OR3
    port map (
      I0 => enc_8b10b_prs_state_fft3_MC_D2_PT_0,
      I1 => enc_8b10b_prs_state_fft3_MC_D2_PT_1,
      I2 => enc_8b10b_prs_state_fft3_MC_D2_PT_2,
      O => enc_8b10b_prs_state_fft3_MC_D2
    );
  enc_8b10b_prs_state_fft3_MC_D_57 : X_XOR2
    port map (
      I0 => enc_8b10b_prs_state_fft3_MC_D_TFF,
      I1 => enc_8b10b_prs_state_fft3_MC_Q,
      O => enc_8b10b_prs_state_fft3_MC_D
    );
  enc_8b10b_prs_state_fft3_MC_XOR : X_XOR2
    port map (
      I0 => enc_8b10b_prs_state_fft3_MC_D1,
      I1 => enc_8b10b_prs_state_fft3_MC_D2,
      O => enc_8b10b_prs_state_fft3_MC_D_TFF
    );
  enc_8b10b_prs_state_fft1_58 : X_BUF
    port map (
      I => enc_8b10b_prs_state_fft1_MC_Q,
      O => enc_8b10b_prs_state_fft1
    );
  enc_8b10b_prs_state_fft1_MC_R_OR_PRLD_59 : X_OR2
    port map (
      I0 => FOOBAR2_ctinst_7,
      I1 => PRLD,
      O => enc_8b10b_prs_state_fft1_MC_R_OR_PRLD
    );
  enc_8b10b_prs_state_fft1_MC_REG : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      I => enc_8b10b_prs_state_fft1_MC_D,
      CE => VCC,
      CLK => clk_II_FCLK,
      SET => GND,
      RST => enc_8b10b_prs_state_fft1_MC_R_OR_PRLD,
      O => enc_8b10b_prs_state_fft1_MC_Q
    );